PCA6416APW,118 NXP Semiconductors, PCA6416APW,118 Datasheet - Page 18

• Manufacturer Part Number: PCA6416APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCA6416APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 200 mA
• Output Current: 10 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
Table 15.
T
[1]
[2]
PCA6416A
Product data sheet
Symbol
(dV/dt)
(dV/dt)
t
V
t
V
d(rst)
w(gl)VDD
amb
POR(trip)
DD(gl)
Level that V
Glitch width that will not cause a functional disruption when V
= 25
f
r

C (unless otherwise noted). Not tested; specified by design.
Recommended supply sequencing and ramp rates
Parameter
fall rate of change of voltage
rise rate of change of voltage
reset delay time
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
DD(P)
can glitch down to with a ramp rate at 0.4 s/V, but not cause a functional disruption when t
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance.
how to measure these specifications.
V
is released and all the registers and the I
their default states. The value of V
0 V.
Fig 19. Glitch width and glitch height
Fig 20. Power-on reset voltage (V
POR
V
V
POR
POR
Figure 20
is critical to the power-on reset. V
(falling V
(rising V
V
DD(P)
DD(P)
DD(P)
∆V
and
All information provided in this document is subject to legal disclaimers.
DD(gl)
V
)
)
POR
DD(P)
Table 15
Condition
Figure 17
Figure 17
Figure
V
Figure
V
Figure 19
Figure 19
falling V
rising V
Rev. 2 — 10 January 2013
DD(P)
DD(P)
w(gl)VDD
Low-voltage translating 16-bit I
drops below 0.2 V or to V
drops to V
17; re-ramp time when
18; re-ramp time when
provide more details on this specification.
DD(P)
DD(P)
DD(gl)
t
w(gl)VDD
) and glitch height (V
POR
POR
= 0.5  V
Figure 19
POR(min)
)
POR
differs based on the V
2
C-bus/SMBus state machine are initialized to
is the voltage level at which the reset condition
DD(P)
 50 mV
and
.
Table 15
SS
DD(gl)
[1]
[2]
2
provide more information on
) are dependent on each
C-bus/SMBus I/O expander
Min
0.1
0.1
1
1
-
-
0.7
-
DD
being lowered to or from
PCA6416A
Typ
-
-
-
-
-
-
-
-
w(gl)VDD
© NXP B.V. 2013. All rights reserved.
< 1 s.
Max
2000
2000
-
-
1.0
10
-
1.4
002aag962
time
002aag963
18 of 42
Unit
ms
ms
s
s
V
s
V
V
time
time