PCA6416AHF,128 NXP Semiconductors, PCA6416AHF,128 Datasheet - Page 11

• Manufacturer Part Number: PCA6416AHF,128
• Description: Interface - I/O Expanders
• Manufacturer: NXP Semiconductors

Specifications of PCA6416AHF,128

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 200 mA
• Output Current: 10 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 6000

NXP Semiconductors
8. Bus transactions
PCA6416A
Product data sheet
7.7 Reset input (RESET)
7.8 Interrupt output (INT)
8.1 Write commands
The RESET input can be asserted to initialize the system while keeping the V
operating level. A reset can be accomplished by holding the RESET pin LOW for a
minimum of t
changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O
levels at the P port can be changed externally or through the master. This input requires a
pull-up resistor to V
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t
changes back to the original value or when data is read from the port that generated the
interrupt (see
or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the
resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to V
V
of the device that requires the interrupt information.
The PCA6416A is an I
PCA6416A through write and read commands using I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
Data is transmitted to the PCA6416A by sending the device address and setting the Least
Significant Bit (LSB) to a logic 0 (see
sent after the address and determines which register receives the data that follows the
command byte.
The eight registers within the PCA6416A are configured to operate as four register pairs.
The four pairs are input ports, output ports, polarity inversion and configuration registers.
After sending data to one register, the next data byte is sent to the other register in the pair
(see
(register 3), the next byte is stored in Output Port 0 (register 2).
There is no limit on the number of data bytes sent in one write transmission. In this way,
the host can continuously update a register pair independently of the other registers or the
host can simply update a single register.
DD(I2C-bus)
Figure 9
v(INT)
depending on the application. INT should be connected to the voltage source
w(rst)
Figure
and
, the signal INT is valid. The interrupt is reset when data on the port
All information provided in this document is subject to legal disclaimers.
. The PCA6416A registers and I
Figure
DD(I2C-bus)
12). Resetting occurs in the Read mode at the acknowledge (ACK)
2
Rev. 2 — 10 January 2013
C-bus slave device. Data is exchanged between the master and
10). For example, if the first byte is sent to Output Port 1
Low-voltage translating 16-bit I
if no active connection is used.
Figure 6
for device address). The command byte is
2
C-bus/SMBus state machine are
2
C-bus. The two communication
2
C-bus/SMBus I/O expander
PCA6416A
© NXP B.V. 2013. All rights reserved.
DD(P)
DD(P)
or
at its
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