821024PP IDT, 821024PP Datasheet

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821024PP

Manufacturer Part Number
821024PP
Description
Interface - CODECs
Manufacturer
IDT
Datasheet

Specifications of 821024PP

Part # Aliases
IDT821024PP
FEATURES
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
4 channel CODEC with on-chip digital filters
Selectable A-law or -law companding
Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and
frame sync signal
Separate PCM and master clocks
Single PCM port with up to 8.192 MHz data rate (128 time slots)
Transhybrid balance impedance hardware adjustable via external
components
Transmit gains hardware adjustable via external components
Low power +5.0 V CMOS technology
+5.0 V single power supply
Package available: 32 pin PLCC, 44 pin TQFP
VOUT2
VOUT3
VOUT4
VOUT1
MCLK
IREF
CNF
IIN2
IIN3
IIN4
IIN1
Reference Circuits
Anolog Front End
Anolog Front End
Anolog Front End
Anolog Front End
QUAD NON-PROGRAMMABLE
PCM CODEC
Clock
CH1
CH2
CH3
CH4
&
DSP
1
DESCRIPTION
chip filters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and
filters in IDT821024 provides the necessary transmit and receive filtering
for voice telephone circuit to interface with time-division multiplexed
systems. All of the digital filters are performed in digital signal processors
operating from an internal clock, which is derived from MCLK. The fixed
filters set the transmit and receive gain and frequency response.
the PCM highway in time slots determined by the individual Frame Sync
signals (FSR
MHz. Both Long and Short Frame Sync modes are available in the
IDT821024.
such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/
Data Access Unit.
The IDT821024 is a single-chip, four channel PCM CODEC with on-
In the IDT821024 the PCM data is transmitted to and received from
The IDT821024 can be used in digital telecommunication applications
n
and FSX
PCM Interface
PCM TSA 1
PCM TSA 2
PCM TSA 3
PCM TSA 4
Control
n
, where n = 1-4) at rates from 256 KHz to 8.192
FEBRUARY 9, 2009
law companding. The digital
PDN 1~ 4
PCLK
A
FSX1
FSR1
FSX2
FSR2
FSX3
FSR3
FSX4
FSR4
TSC
DR
DX
IDT821024
DSC-6034/4

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821024PP Summary of contents

Page 1

... Anolog Front End IIN4 VOUT4 MCLK IREF Reference Circuits CNF The IDT logo is a registered trademark of Integrated Device Technology, Inc INDUSTRIAL TEMPERATURE RANGE 2003 Integrated Device Technology, Inc. QUAD NON-PROGRAMMABLE PCM CODEC DESCRIPTION The IDT821024 is a single-chip, four channel PCM CODEC with on- chip filters ...

Page 2

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC PIN CONFIGURATIONS IIN1 IIN2 VOUT2 VCCA IREF AGND VOUT3 IIN3 IIN4 1 IIN2 2 VOUT2 VCCA 6 IREF 7 AGND VOUT3 11 IIN3 32-Pin 9 PLCC 44-Pin TQFP 2 INDUSTRIAL TEMPERATURE RANGE PCLK 29 TSC 28 DGND ...

Page 3

... IREF pin. Master Clock. The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The IDT821024 determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the FSX frequency. ...

Page 4

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC PIN DESCRIPTION (cont’d) Pin Number Name I/O PLCC TQFP PDN1 2 39 PDN2 PDN3 32 37 PDN4 31 36 CNF 14, 15, 17 29, 32, 33, 40, 42 Channel 1/2/3/4 Power Down. When this pin is high, Channel N is powered down. ...

Page 5

... PCM frame for Channel N. The PCM Data is received serially on DR pin with the Most Significant Bit (MSB) first. Hardware Gain Setting In Transmit Path The transmit gain of the IDT821024 for each channel can be set by 2 resistors, R ing equation: The receive gain of IDT821024 is fixed and equal to 1. ...

Page 6

... PDNn is 0, Channel normal mode. In standby mode, all circuits are powered down with the analog outputs placed in high impedance state. In normal mode, each channel of the IDT821024 is able to transmit and receive both PCM and analog information. The normal mode is used when a telephone call is in progress. ...

Page 7

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC ABSOLUTE MAXIMUM RATINGS Rating Com’I & Ind’I Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 8

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC TRANSMISSION CHARACTERISTICS 0dBm0 is defined as 0.6832Vrms for A-law and 0.6778 Vrms for -law, both for 600 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder ...

Page 9

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC Distortion Parameter Description STD Transmit Signal to Total Distortion Ratio X A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 -law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 STD ...

Page 10

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC Interchannel Crosstalk Parameter Description XT Transmit to Receive Crosstalk X-R XT Receive to Transmit Crosstalk R-X XT Transmit to Transmit Crosstalk X-X XT Receive to Receive Crosstalk R-R Intrachannel Crosstalk Parameter Description XT Transmit to Receive Crosstalk X-R XT Receive to Transmit Crosstalk R-X Min Typ Max Units 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel. ...

Page 11

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC TIMING CHARACTERISTICS Clock Parameter Description t1 PCLK Duty Cycle t2 PCLK Rise and Fall Time t3 MCLK Duty Cycle t4 MCLK Rise and Fall Time t5 PCLK Clock Period Transmit Parameter Description t11 Data Output Delay Time (for Short Frame Sync Mode) ...

Page 12

... IDT821024 QUAD NON-PROGRAMMABLE PCM CODEC PCLK t15 FSX/ FSR DX DR TSC Figure 3. PCM Interface Timing for Short Frame Mode PCLK FSX/ FSR DX DR TSC Figure 4. PCM Interface Timing for Long Frame Mode Time Slot t14 t2 t11 BIT 1 BIT 3 BIT 4 ...

Page 13

... X Process/ Package Temperature Range for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* The IDT logo is a registered trademark of Integrated Device Technology, Inc. 13 Blank Industrial (-40 °C to +85 °C) J Plastic Leaded Chip Carrier (PLCC, PL32) PP Thin Quad Flat Pack (TQFP, PP44) 821024 Quad Non-Programmable PCM CODEC for Tech Support: email: telecomhelp@idt ...

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