SST39VF160-70-4I-BK Microchip Technology, SST39VF160-70-4I-BK Datasheet - Page 3

• Manufacturer Part Number: SST39VF160-70-4I-BK
• Description: Flash 1M X 16 70ns
• Manufacturer: Microchip Technology

Specifications of SST39VF160-70-4I-BK

• Product Category: Flash
• Data Bus Width: 16 bit
• Memory Type: NOR Flash
• Memory Size: 16 Mbit
• Architecture: Sectored
• Interface Type: Parallel
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 20 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TFBGA
• Organization: 4 KB x 512

16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data# Polling (DQ
When the SST39LF/VF160 are in the internal Program
operation, any attempt to read DQ
plement of the true data. Once the Program operation is
completed, DQ
though DQ
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ
internal Erase operation is completed, DQ
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
tor-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39LF/VF160 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2003 Silicon Storage Technology, Inc.
DD
Power Up/Down Detection: The Write operation is
7
may have valid data immediately following the
7
DD
will produce true data. Note that even
is less than 1.5V.
6
)
7
)
7
6
will produce a ‘0’. Once the
will produce alternating 1s
7
will produce the com-
7
will produce a
6
bit will
3
Software Data Protection (SDP)
The SST39LF/VF160 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to Read mode within T
DQ
command sequence.
Common Flash Memory Interface (CFI)
The SST39LF/VF160 also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must load the three-byte
sequence, similar to the Software ID Entry command. The
last byte cycle of this command loads 98H (CFI Query
command) to address 5555H. Once the device enters the
CFI Query mode, the system can read CFI data at the
addresses given in Tables 5 through 7. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as
the SST39LF/VF160 and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify the
part (i.e., using the device ID) when using multiple manu-
facturers in the same socket. For details, see Table 4 for
software operation, Figure 11 for the Software ID Entry and
Read timing diagram, and Figure 18 for the Software ID
Entry command sequence flowchart.
TABLE 1: P
Manufacturer’s ID
Device ID
8
SST39LF/VF160
can be V
IL
RODUCT
or V
IH
, but no other value, during any SDP
I
DENTIFICATION
RC
. The contents of DQ
Address
0000H
0001H
S71145-04-000 11/03 399
Data Sheet
00BFH
2782H
Data
T1.2 399
15
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