IS25WD020-JNLE ISSI, IS25WD020-JNLE Datasheet
IS25WD020-JNLE
Specifications of IS25WD020-JNLE
Related parts for IS25WD020-JNLE
IS25WD020-JNLE Summary of contents
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... Typical 7 ms sector, block or chip erase GENERAL DESCRIPTION The IS25WD020/040 are 2 Mbit / 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 30 MHz fclock rate in normal read mode, and 80 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from 1 ...
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... HOLD# INPUT Hold: Pause serial communication by the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 Vcc CE HOLD# 3 WP# SCK 4 GND SIO 8-Contact WSON IS25WD020/040 8 Vcc 7 HOLD# 6 SCK SIO 5 2 ...
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... BLOCK DIAGRAM SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 3 ...
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... SPI MODES DESCRIPTION Multiple IS25WD020/040 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) ...
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... Figure 2. SPI Modes Supported SCK Mode 0 (0, 0) SCK Mode 3 (1, 1) SIO MSb Input mode SO Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 MSb 5 ...
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... SYSTEM CONFIGURATION The IS25WD020/040 devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The devices have two superset features that can be enabled through specific software instructions and the Configuration Register: Table 1 illustrates the memory map of the devices ...
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... WRSR instruction will be ignored. If the SRWD is set to “1” and WP# is pulled high (V Register can be changed by a WRSR instruction. Bit 6 Bit 5 Bit 4 Bit 3 Reserved BP2 BP1 IS25WD020/040 ), the volatile bits of Status IL ), the Status IH Bit 2 Bit 1 Bit 0 BP0 WEL WIP 0 0 ...
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... N/A Status Register Write Disable: (See Table 9 for details) “0” indicates the Status Register is not write-protected (default) Bit 7 SRWD “1” indicates the Status Register is write-protected Table 8. Block Write Protect Bits for IS25WD020 Status Register Bits BP2 BP1 Not used 0 Not used ...
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... REGISTERS (CONTINUED) PROTECTION MODE The IS25WD020/040 have two types of write- protection mechanisms: hardware and software. These are used to prevent irrelevant operation in a possibly noisy environment and protect the data integrity. HARDWARE WRITE-PROTECTION The devices provide two hardware write-protection features: a. When inputting a program, erase or write status ...
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... DEVICE OPERATION The IS25WD020/040 utilize an 8-bit instruction register. Refer to Table 10 Instruction Set for details of the Instructions and Instruction Codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on Serial Data Input (SI). The input data latched on the rising edge of Serial ...
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... SCK while CE low. Table 11. Product Identification Product Identification Manufacturer ID Device ID: IS25WD020 IS25WD040 Dummy Bytes Device ID1 IS25WD020/040 Data First Byte Second Byte Device ID 1 Device ID 2 11h 12h Device ID1 Device ID1 ...
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... Rev. D 2/12/2013 by the first Manufacturer ID (9Dh) and the Device ID (32h, in the case of the IS25WD020), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 the Device ID (32h, in the case of the IS25WD020), and is shifted out on SO with the MSB first, each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high ...
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... ADDRESS will output the 1 0. ADDRESS will output the device ID1 -> 1 Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 manufacture ID (9Dh) first -> device ID1 -> manufacture ID (9D) -> 2 IS25WD020/040 nd manufacture ID (7Fh) nd manufacture ID (7Fh) 14 ...
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... WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the IS25WD020/040 is reset to the write –protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block Figure 6 ...
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... Figure 9. Write Status Register Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register. or “1” s into the volatile BP2, BP1, BP0 and SRWD bits. ...
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... DEVICE OPERATION (CONTINUED) READ COMMAND (READ DATA) OPERATION The Read Data (READ) instruction is used to read memory data of a IS25WD020/040 under normal mode running MHz. The READ instruction code is transmitted via the Sl line, followed by three address bytes (A23 – A0) of the first memory location to be read ...
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... The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FAST_READ instruction. The FAST_READ instruction is terminated by driving CE# , during high ( IS25WD020/040 18 ...
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... FRDO instruction. FRDO instruction is terminated by driving CE# high ( BYTE ADDRESS DATA OUT IS25WD020/040 ). ... ... DATA OUT ...
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... Figure 15. Page Program Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. If more than 256 bytes data are sent to a device, the ...
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... DEVICE OPERATION (CONTINUED) ERASE OPERATION The memory array of the IS25WD020/040 is organized into uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (a block consists of sixteen adjacent sectors). Before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”). In order to erase the devices, there are ...
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... DEVICE OPERATION (CONTINUED) Figure 16. Sector Erase Sequence SIO Figure 17. Block Erase Sequence SIO Figure 18. Chip Erase Sequence SIO Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 22 ...
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... Halogen-free Package 260 o Lead-free Package 260 -0 VCC + 0 VCC + 0 0.5 V. During voltage transitions, input or I/O pins may CC IS25WD020/040 +125 +125 Seconds C 10 Seconds IS25WD020/040 105 - - 105 -40 ...
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... CE 1.95V 1.65V < V < 1.95V CC = -100 IS25WD020/040 Min Typ Max Units A 1 A 1 -0.5 0 0.7V CC 0.3 0.2 – 0.2 24 ...
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... HZ t Output Disable Time DIS t Sector/Block/Chip Erase Time EC t Page Program Time Set-up Time VCS CC t Write Status Register time w Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 = 1. 1. Min Typ Max ...
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... AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING SIO Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 (1) IS25WD020/040 26 ...
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... AC CHARACTERISTICS (CONTINUED) HOLD TIMING PIN CAPACITANCE ( MHz 25°C ) Typ OUT Note: These parameters are characterized but not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 Max Units IS25WD020/040 Conditions OUT 27 ...
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... At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. All Write Commands are Rejected tVCE tPUW Parameter IS25WD020/040 Read Access Allowed Device fully accessible Time Min. Max. Unit 10 us ...
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... From writing erase command to erase completion 2 3 From writing program command to program completion Min Unit Test Method 200,000 Cycles JEDEC Standard A117 20 Years JEDEC Standard A103 2,000 Volts JEDEC Standard A114 200 Volts JEDEC Standard A115 100 + I mA JEDEC Standard 78 CC1 IS25WD020/040 29 ...
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... PACKAGE TYPE INFORMATION JN 8-Pin SOIC 150mil Broad Small Outline Integrated Circuit Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 30 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JV 8-Pin VVSOP 150mil (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 31 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 32 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JB 8-Pin SOIC 208mil Broad Small Outline Integrated Circuit Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 33 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JK 8-pin WSON Ultra-Thin Small Outline No-Lead Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 34 ...
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... PRODUCT ORDERING INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 35 ...
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... ORDERING INFORMATION: Frequency Density Order Part Number (MHz) IS25WD020-JBLE IS25WD020-JNLE IS25WD020-JVLE IS25WD020-JKLE 2M 80 IS25WD020-JBLA* IS25WD020-JNLA* IS25WD020-JVLA* IS25WD020-JKLA* IS25WD020-JWLE IS25WD040-JNLE IS25WD040-JBLE IS25WD040-JVLE IS25WD040-JKLE 4M 80 IS25WD040-JNLA* IS25WD040-JBLA* IS25WD040-JVLA* IS25WD040-JKLA* IS25WD020-JWLE A* = A1, A2 Automotive Temperature Ranges Integrated Silicon Solution, Inc.- www.issi.com Rev. D 2/12/2013 IS25WD020/040 Package ...