GLS36VF3204-70-4E-EKE Greenliant, GLS36VF3204-70-4E-EKE Datasheet - Page 3

• Manufacturer Part Number: GLS36VF3204-70-4E-EKE
• Description: Flash 2Mx16 or 4Mx8 70ns
• Manufacturer: Greenliant

Specifications of GLS36VF3204-70-4E-EKE

• Rohs: yes
• Data Bus Width: 8 bit, 16 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-48
• Organization: 2 MB x 16, 4 MB x 8

32 Mbit Concurrent SuperFlash
GLS36VF3203 / GLS36VF3204
See Figures 5 and 6 for WE# and CE# controlled Program
operation timing diagrams and Figure 20 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.
Sector- (Block-) Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (50H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (30H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 10 and 11 for timing waveforms.
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid Read is Toggle Bit or Data# Poll-
ing. Any commands issued during the Chip-Erase opera-
tion are ignored. See Table 7 for the command sequence,
Figure 9 for timing diagram, and Figure 23 for the flowchart.
When WP# is low, any attempt to Chip-Erase will be
ignored.
©2010 Greenliant Systems, Ltd.
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
3
Erase-Suspend/Erase-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (T
maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ
DQ
operation is allowed except for the sector or block selected
for Erase-Suspend. The Software ID Entry command can
also be executed. To resume Sector-Erase or Block-Erase
operation which has been suspended, the system must
issue an Erase-Resume command. The operation is exe-
cuted by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the last
byte sequence.
Write Operation Status Detection
These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy#
(RY/BY#), a Data# Polling (DQ
may be simultaneous with the completion of the Write
cycle. If this occurs, the system may get an erroneous
result, i.e., valid data may appear to conflict with either DQ
or DQ
ous result occurs, the software routine should include a
loop to read the accessed location an additional two (2)
times. If both Reads are valid, then the Write cycle has
completed, otherwise the rejection is valid.
6
at “1”. While in Erase-Suspend mode, a Program
6
. In order to prevent spurious rejection if an errone-
7
) and Toggle Bit (DQ
7
), or Toggle Bit (DQ
S71270-05-000
2
toggling and
Data Sheet
6
6
) Read
). The
05/10
ES
7