78Q2123/F1 Maxim Integrated, 78Q2123/F1 Datasheet - Page 5

• Manufacturer Part Number: 78Q2123/F1
• Description: Ethernet ICs
• Manufacturer: Maxim Integrated

Specifications of 78Q2123/F1

• Rohs: yes

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Chip power-down is activated by setting the PWRDN bit in MII register MR0.11. When the chip is in
power-down mode, all on-chip circuitry is shut off, and the device consumes minimum power. While in
the power-down state, the 78Q2123/78Q2133 still respond to management transactions.
Receive power management (RXCC mode) is activated by setting the RXCC bit in MII register MR16.0.
In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all other
receive circuitry will be powered down when no valid MLT-3 signal is present at the UTP receive line
interface. As soon as a valid signal is detected, all circuits will automatically be powered up to resume
normal operation. During this mode of operation, RX_CLK will be inactive when there is no data being
received. Note that the RXCC mode is not supported during 10BASE-T operation.
Transmit high impedance mode is activated by setting the TXHIM bit in MII register MR16.12. In this
mode of operation, the transmit UTP drivers are in a high impedance state and TX_CLK is tri-stated. A
weak internal pull-up is enabled on TX_CLK. The receive circuitry remains fully operational. The default
state of MR16.12 is a logic low for disabling the transmit high impedance mode. Only a reset condition will
automatically clear MR16.12. The transmitter is fully functional when MR16.12 is cleared. This feature is
useful when configuring a system for Wake-On LAN (when the 78Q2123/78Q2133 are coupled with a
Wake-On LAN capable MAC).
High accuracy is maintained through a closed-loop trimmed biasing network.
On-chip digital logic runs off an internal voltage regulator. Hence only a single 3.3V (± 0.3V) supply is
required to power-up the device. The on-chip regulator is not affected by the power-down mode.
25 MHz clock by 4/5. The synthesizer references either the local 25 MHz crystal oscillator, or the externally
applied clock, depending on the selected mode of operation.
DS_21x3_001
1 Functional Description
1.1
1.1.1 Power Management
The 78Q2123 and 78Q2133 have three power saving modes:
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1.1.2 Analog Biasing and Supply Regulation
The 78Q2123/78Q2133 require no external component to generate on-chip bias voltages and currents.
1.1.3 Clock Selection
The 78Q2123/78Q2133 have an on-chip crystal oscillator which can also be driven by an external oscillator.
In this mode of operation, a 25 MHz crystal should be connected between the XTLP and XTLN pins.
Alternatively, an external 25 MHz clock input can be connected to the XTLP pin. In this mode of operation,
a crystal is not required and the XTLN pin must be tied to ground.
1.1.4 Transmit Clock Generation
The transmitter uses an on-chip frequency synthesizer to generate the transmit clock. In 100BASE-TX
operation, the synthesizer multiplies the reference clock by 5 to obtain the internal 125 MHz serial transmit
clock. In 10BASE-T mode, it generates an internal 20MHz transmit clock by multiplying the reference
Rev. 1.6
Chip Power-Down
Receive Power Management
Transmit High Impedance Mode
General
78Q2123/78Q2133 Data Sheet
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