1893YI-10LF IDT, 1893YI-10LF Datasheet - Page 138
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1893YI-10LF
Manufacturer Part Number
1893YI-10LF
Description
Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
Manufacturer
IDT
Datasheet
1.1893Y-10LFT.pdf
(152 pages)
Specifications of 1893YI-10LF
Rohs
yes
Part # Aliases
ICS1893YI-10LF
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10.5.12 MII / 100M Stream Interface: Transmit Latency
ICS1893 Rev C 6/6/00
TXEN
TXCLK
TXD
TP_TX
Table 10-19
periods consist of timings of signals on the following pins:
•
•
•
•
Figure 10-13
Table 10-19. MII / 100M Stream Interface Transmit Latency
† The IEEE maximum is 18 bit times.
Figure 10-13.
Period
†
unscrambled.
Time
TXEN
TXCLK
TXD (that is, TXD[3:0])
TP_TX (that is, TP_TXP and TP_TXN)
Shown
t1
t2
ICS1893 Data Sheet - Release
†
TXEN Sampled to MDI Output of First
Bit of /J/ †
TXD Sampled to MDI Output of First
Bit of /J/ †
lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
shows the timing diagram for the time periods.
Preamble /J/
MII / 100M Stream Interface Transmit Latency Timing Diagram
Parameter
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Preamble /K/
t1
t2
138
MII mode
100M Stream Interface
Conditions
Chapter 10 DC and AC Operating Conditions
Min.
–
–
Typ. Max.
2.8
6.1
3
7
Bit times
Bit times
June, 2000
Units
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