KSZ8842-16MVL TR Micrel, KSZ8842-16MVL TR Datasheet - Page 76
![no-image](/images/no-image-200.jpg)
KSZ8842-16MVL TR
Manufacturer Part Number
KSZ8842-16MVL TR
Description
Ethernet ICs 2-Port Ethernet Switch/Repeater + Generic (8, 16-bit) bus interface(Lead Free)
Manufacturer
Micrel
Datasheet
1.KSZ8842-16MVL_TR.pdf
(141 pages)
Specifications of KSZ8842-16MVL TR
Rohs
yes
Product
Ethernet Switches
Package / Case
PQFP-128
Mounting Style
SMD/SMT
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Bank 32 Switch Global Control Register 3 (0x06): SGCR3
This register contains the global control for the switch function.
Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63.
Note 1: User has to set bit 13 (100Mbps), bit 12 (auto-negotiation disabled) and bit 8 (half duplex) in both P1MBCR and
P2MBCR registers for repeater mode.
Bank 32 Switch Global Control Register 4 (0x08): SGCR4
This register contains the global control for the switch function.
Micrel, Inc.
Bit
15-8
7
6
5
4
3
2-0
Bit
15-0
October 2007
Default
0
0
0
0
0
Default
0x63
0x0
0x2400
R/W
RW
RW
RW
RW
RW
RW
RW
R/W
RW
Description
Broadcast Storm Protection Rate Bit [7:0]
These bits, along with SGCR3[2:0], determine how many 64-byte blocks of packet
data are allowed on an input port in a preset period. The period is 67ms for 100BT or
670ms for 10BT. The default is 1%.
Repeater Mode (Note 1)
1 = enable repeater mode.
0 = normal mode.
The switch supports only half duplex , 100BT in repeater mode.
Switch Host Half-Duplex Mode
The KSZ8842M supports only half-duplex 100-BaseT throughput in repeater mode.
1 = enable host port interface half-duplex mode, this bit must be set for repeater mode
0 = enable host port interface full-duplex mode..
Switch Flow Control Enable
1 = enable full-duplex flow control on Switch Host port.
0 = disable full-duplex flow control on Switch Host port
Reserved
Null VID Replacement
1 = replaces NULL VID with port VID(12 bits).
0 = no replacement for NULL VID.
Broadcast Storm Protection Rate Bit [10:8]
These bits, along with SGCR3[15:8] determine how many 64-byte blocks of packet
data are allowed on an input port in a preset period. The period is 67ms for 100BT or
670ms for 10BT. The default is 1%.
Description
Reserved
76
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9
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