KSZ8842-16MVL TR Micrel, KSZ8842-16MVL TR Datasheet - Page 24

• Manufacturer Part Number: KSZ8842-16MVL TR
• Description: Ethernet ICs 2-Port Ethernet Switch/Repeater + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8842-16MVL TR

• Rohs: yes
• Product: Ethernet Switches
• Package / Case: PQFP-128
• Mounting Style: SMD/SMT

Micrel, Inc.
October 2007
Pin Number
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DATACSN
Pin Name
CYCLEN
VLBUSN
P2LED3
SRDYN
VDDCO
LDEVN
INTRN
DGND
EECS
ARDY
BCLK
RDN
NC
Type
Opu
Opu
Opd
Opd
Opu
Opd
Opd
Gnd
Ipd
Ipu
Ipd
Ipd
Ipd
P
Pin Function
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
DATA Chip Select Not (For KSZ8842-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
When DATACSN is Low, the data path can be accessed regardless of the value
of AEN, A15-A1, and the content of the BANK select register.
No connect.
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8842M drives this pin low to
signal wait states.
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this pin
need an external 4.7K pull-up resistor.
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8842M address programmed into the high byte of the base address register.
LDEVN is a combinational decode of the Address and AEN signal.
Read Strobe Not
Asynchronous read strobe, active Low.
EEPROM Chip Select
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access
cycles. It is asynchronous to the host CPU or bus clock. this pin need an
external 4.7K pull-up resistor.
Cycle Not
For VLBus-like mode cycle signal; this pin follows the addressing cycle to signal
the command cycle.
For burst mode (32-bit interface only), this pin stays High for read cycles and
Low for write cycles.
Port 2 LED indicator.
See the description in pins 6, 7, and 8.
Digital IO ground
1.2V digital core voltage output (internal 1.2V LDO power supply output), this
1.2V output pin provides power to VDDC, VDDA and VDDAP pins.
Note: Internally generated power voltage. Do not connect an external power
supply to this pin. This pin is used for connecting external filter (Ferrite Bead and
capacitors). It is recommended this pin should be connected to 3.3V power rail by
a 100 ohm resistor for the internal LDO application.
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 32-bit asynchronous mode or EISA-like
burst mode.
24
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9