iCE65L01F-LQN84C Lattice, iCE65L01F-LQN84C Datasheet - Page 2

• Manufacturer Part Number: iCE65L01F-LQN84C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LQN84C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 67
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-84
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 260

iCE65 Ultra Low-Power mobileFPGA
Overview
(2.42, 30-MAR-2012)
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The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and
dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for cost-
sensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize
for a specific application. iCE65 devices can self-configure from a configuration image stored in an external
commodity SPI serial Flash PROM or be downloaded from an external processor over an SPI-like serial port.
The three iCE65 components, highlighted in
flops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65 device
includes between 16 to 32 RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering.
As pictured in
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An array of Programmable Logic Blocks (PLBs)
Two-port, 4Kbit RAM blocks (RAM4K)
Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO)
blocks
Programmable interconnections between the blocks
Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …
Common clock input with polarity control, clock-enable input, and optional set/reset control input to
the PLB is shared among all eight Logic Cells
256x16 default configuration; selectable data width using programmable logic resources
Simultaneous read and write access; ideal for FIFO memory and data buffering applications
RAM contents pre-loadable during configuration
LVCMOS I/O standards and LVDS outputs supported in all banks
I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards
Flexible connections between all programmable logic functions
Eight dedicated low-skew, high-fanout clock distribution networks
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Figure
A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of
up to four inputs, regardless of complexity
A ‘D’-type flip-flop with an optional clock-enable and set/reset control
Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and
counters.
1, each iCE65 device consists of four primary architectural elements.
Table 1,
™
deliver from approximately 1K to nearly 8K logic cells and flip-
Family
Lattice Semiconductor Corporation
www.latticesemi.com