iCE65L04F-TCB284I Lattice, iCE65L04F-TCB284I Datasheet - Page 34

• Manufacturer Part Number: iCE65L04F-TCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-TCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

iCE65 Ultra Low-Power mobileFPGA
(2.42, 30-MAR-2012)
34
Warm Boot Configuration Option
Time-Out and Retry
SPI Peripheral Configuration Interface
When creating the initial configuration image, the Lattice development software loads the start address for up to
four configuration images in the bitstream. The value on the CBSEL[1:0] pins tell the configuration controller to
read a specific start address, then to load the configuration image stored at the selected address. The multiple
bitstreams are stored either in the SPI Flash or in the internal NVCM.
After configuration, the CBSEL[1:0] pins become normal PIO pins available to the application.
The Cold Boot feature allows the iCE65 to be reprogrammed for special application requirements such as the
following.
The Warm Boot configuration is similar to the Cold Boot feature, but is completely under the control of the FPGA
application.
A special design primitive, SB_WARMBOOT, allows an FPGA application to choose between four configuration
images using two internal signal ports, S1 and S0, as shown in
programmable interconnect, which in turn can connect to PLB logic and/or PIO pins.
After selecting the desired configuration image, the application then asserts the internal signal BOOT port High to
force the FPGA to restart the configuration process from the specified vector address stored in PROM.
When configuring from external SPI Flash, the iCE65 device looks for a synchronization word. If the device does
not find a synchronization word within its timeout period, the device automatically attempts to restart the
configuration process from the very beginning. This feature is designed to address any potential power-sequencing
issues that may occur between the iCE65 device and the external PROM.
The iCE65 device attempts to reconfigure six times. If not successful after six attempts, the iCE65 FPGA
automatically goes into low-power mode.
Using the SPI peripheral configuration interface, an application processor (AP) serially writes a configuration image
to an iCE65 FPGA using the iCE65’s SPI interface, as shown in
a separate, independent I/O bank, powered by the VCC_SPI supply input. Typically, VCC_SPI is the same voltage as
the application processor’s I/O. The configuration control signals, CDONE and CRESET_B, are supplied by the
separate I/O Bank 2 voltage input, VCCIO_2.
This same SPI peripheral interface supports programming for the iCE65’s Nonvolatile Configuration Memory
(NVCM).
ColdBoot Select
PIO2/CBSEL0
PIO2/CBSEL1



!
A normal operating mode and a self-test or diagnostics mode.
Different applications based on switch settings.
Different applications based on a card-slot ID number.
A Warm Boot application can only jump to another configuration image that DOES NOT have Warm
Boot enabled. There is no such restriction for Cold Boot applications.
Table 28:
CB81
G5
H5
ColdBoot Select Ball/Pin Numbers by Package
QN84
B15
A20
™
Family
VQ100
41
42
Figure
Figure
23. The iCE65’s SPI configuration interface is
27. These internal signal ports connect to
CB132
P10
L9
Lattice Semiconductor Corporation
CB196
P10
L9
www.latticesemi.com
CB284
R13
V14