iCE65L04F-TCB284I Lattice, iCE65L04F-TCB284I Datasheet - Page 10

• Manufacturer Part Number: iCE65L04F-TCB284I
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-TCB284I

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 176
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-284
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 168

iCE65 Ultra Low-Power mobileFPGA
Programmable Input/Output Block (PIO)
(2.42, 30-MAR-2012)
10
I/O Banks
Programmable Input/Output (PIO) blocks surround the periphery of the device and connect external components to
the Programmable Logic Blocks (PLBs) and RAM4K blocks via programmable interconnect. Individual PIO pins are
grouped into one of four I/O banks, as shown in
differential I/O and the ability to interface to Mobile DDR memories.
Figure 7
output, or a bidirectional I/O pin with a separate direction control input.
PIO blocks are organized into four separate I/O banks, each with its own voltage supply input, as shown in
The voltage applied to the VCCIO pin on a bank defines the I/O standard used within the bank.
51
devices, I/O Bank 3, along the left edge of the die, is different than the others and supports specialized I/O standards.
I/O Bank Voltage Supply Inputs Support Different I/O Standards
Because each I/O bank has its own voltage supply, iCE65 components become the ideal bridging device between
different interface standards. For example, the iCE65 device allows a 1.8V-only processor to interface cleanly with a
3.3V bus interface. The iCE65 device replaces external voltage translators.
describe the I/O drive capabilities and switching thresholds by I/O standard. On iCE65L04 and iCE65L08
Bank
SPI
0
1
2
3
also shows the logic within a PIO pin. When used in an application, a PIO pin becomes a signal input, an
VCC
Internal Core
Bottom Right
Device Edge
Bottom
General-Purpose I/O
Right
Top
Left
General-Purpose I/O
I/O Bank 0
I/O Bank 2
Figure 7:
VCCIO_0
VCCIO_2
Table 5: Supported Voltages by I/O Bank
Supply Input
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
Programmable Input/Output (PIO) Pin
SPI_VCC
Config
SPI
PIO
Figure
™
OUT
Family
IN
OE
3.3V
Yes
Yes
Yes
Yes
Yes
7. I/O Bank 3 has additional capabilities, including LVDS
iCEGATE
Disabled
HOLD
Enabled
= Statically defined by configuration program
Programmable Input/Output
2.5V
Yes
Yes
Yes
Yes
Yes
‘1’
‘0’
HD
Lattice Semiconductor Corporation
I/O Bank 0, 1, or 2
Latch inhibits
switching for
lowest power
Voltage Supply
0 = Hi-Z
1 = Output
1.8V
GBIN pins optionally
connect directly to an
associated GBUF global
buffer
Yes
Yes
Yes
Yes
Yes
Enabled
VCCIO
iCE65L01: Outputs only
Pull-up
Enable
www.latticesemi.com
iCE65L04/08: Yes
1.5V to 3.3V
Pull-up
not in I/O
Bank 3
Table 50
Outputs only
Outputs only
Outputs only
PAD
1.5V
No
and
Table
Table
5.