LFXP20C-3F484C Lattice, LFXP20C-3F484C Datasheet - Page 62
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LFXP20C-3F484C
Manufacturer Part Number
LFXP20C-3F484C
Description
FPGA - Field Programmable Gate Array 19.7K LUTs 340 I/O 1.8/2.5/3.3V -3 Spd
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T144C.pdf
(130 pages)
Specifications of LFXP20C-3F484C
Number Of I/os
340
Maximum Operating Frequency
320 MHz
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-484
Minimum Operating Temperature
0 C
Factory Pack Quantity
300
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Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
Notes:
1. “n” is a row/column PIC number.
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR
3. The definition of the PIC numbering is provided in the Signal Names column of the Signal Descriptions table in this data sheet.
data (DQ) pins may not be available.
with DQS Strobe
PICs Associated
PIO within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
4-3
Complement
Complement
Complement
Complement
Complement
Complement
Complement
Polarity
True
True
True
True
True
True
True
LatticeXP Family Data Sheet
Pinout Information
and Data (DQ) Pins
DDR Strobe (DQS)
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
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