LFXP20C-3F484C Lattice, LFXP20C-3F484C Datasheet - Page 22

• Manufacturer Part Number: LFXP20C-3F484C
• Description: FPGA - Field Programmable Gate Array 19.7K LUTs 340 I/O 1.8/2.5/3.3V -3 Spd
• Manufacturer: Lattice

Specifications of LFXP20C-3F484C

• Number Of I/os: 340
• Maximum Operating Frequency: 320 MHz
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-484
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-23. Output Register Block
Figure 2-24. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Routing
From
ONEG0
OPOS0
CLK1
*Latch is transparent when input is low.
CLK
LSR
DA
DB
/LATCH
D
D
D-Type
LATCH
LE*
ODDRXB
2-19
Q
Q
Q
0
1
Programmed
Control
LatticeXP Family Data Sheet
OUTDDN
0
1
To sysIO
Buffer
DO
Architecture