LFE2-6E-5T144C Lattice, LFE2-6E-5T144C Datasheet - Page 75

• Manufacturer Part Number: LFE2-6E-5T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -5
• Manufacturer: Lattice

Specifications of LFE2-6E-5T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 311 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

LatticeECP2 sysCONFIG Port Timing Specifications
Lattice Semiconductor
sysCONFIG Byte Data Flow
t
t
t
t
t
t
t
t
t
sysCONFIG Byte Slave Clocking
t
t
t
sysCONFIG Serial (Bit) Data Flow
t
t
t
t
t
sysCONFIG Serial Slave Clocking
t
t
sysCONFIG POR, Initialization and Wake-up
t
t
t
t
t
t
t
t
t
t
sysCONFIG SPI Port
t
t
t
t
t
t
SUCBDI
HCBDI
CODO
SUCS
HCS
SUWD
HWD
DCB
CORD
BSCH
BSCL
BSCYC
SUSCDI
HSCDI
CODO
SUMCDI
HMCDI
SSCH
SSCL
ICFG
VMC
PRGMRJ
PRGM
DINIT
DPPINIT
DPPDONE
IODISS
IOENSS
MWC
CFGX
CSSPI
CSCCLK
SOCDO
SOE
CSPID
Parameter
Byte D[0:7] Setup Time to CCLK
Byte D[0:7] Hold Time to CCLK
CCLK to DOUT in Flowthrough Mode
CSN[0:1] Setup Time to CCLK
CSN[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
CCLK to Out for Read Data
Byte Slave CCLK Minimum High Pulse
Byte Slave CCLK Minimum Low Pulse
Byte Slave CCLK Cycle Time
DI Setup Time to CCLK Slave Mode
DI Hold Time to CCLK Slave Mode
CCLK to DOUT in Flowthrough Mode
DI Setup Time to CCLK Master Mode
DI Hold Time to CCLK Master Mode
Serial Slave CCLK Minimum High Pulse
Serial Slave CCLK Minimum Low Pulse
Minimum Vcc to INITN High
Time from t
PROGRAMN Pin Pulse Rejection
PROGRAMN Low Time to Start Configuration
PROGRAMN High to INITN High Delay
Delay Time from PROGRAMN Low to INITN Low
Delay Time from PROGRAMN Low to DONE Low
User I/O Disable from PROGRAMN Low
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
Additional Wake Master Clock Signals after DONE Pin High
INITN High to CCLK Low
INITN High to CSSPIN Low
CCLK Low before CSSPIN Low
CCLK Low to Output Valid
CSSPIN[0:1] Active Setup Time
CSSPIN[0:1] Low to First CCLK Edge Setup Time
ICFG
to Valid Master CCLK
Over Recommended Operating Conditions
Description
3-28
DC and Switching Characteristics
LatticeECP2 Family Data Sheet
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
cycles
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
µs
us
ns
ns
ns
ns