LFE2-6E-5T144C Lattice, LFE2-6E-5T144C Datasheet - Page 74

• Manufacturer Part Number: LFE2-6E-5T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -5
• Manufacturer: Lattice

Specifications of LFE2-6E-5T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 311 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
DLL Timing
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
REF
FB
CLKOP
CLKOS
PJIT
CYJIT
DUTY
DUTYTRD
DUTYCIR
SKEW
PHASE
PWH
PWL
R
INSTB
LOCK
RSWD
PA
RANGE1
RANGE4
Parameter
, t
F
3
1
2
Input reference clock frequency (on-chip or off-chip)
Feedback clock frequency (on-chip or off-chip)
Output clock frequency, CLKOP
Output clock frequency, CLKOS
Output clock period jitter (clean input)
Output clock cycle to cycle jitter (clean input)
Output clock duty cycle (at 50% levels, 50% duty cycle input clock, 50%
duty cycle circuit turned off, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50%
duty cycle circuit enabled, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50%
duty cycle circuit enabled, clock injection removal mode)
Output clock to clock skew between two outputs with the same phase set-
ting
Phase error measured at device pads using off-chip reference clock and
feedback clocks
Input clock minimum pulse width high (at 80% level)
Input clock minimum pulse width low (at 20% level)
Input clock rise and fall time (20% to 80% levels)
Input clock period jitter
DLL lock time (input stable until assertion of LOCK)
Digital reset minimum pulse width (at 80% level)
Delay step size
Max. delay setting for single delay block (144 taps)
Max. delay setting for four chained delay blocks
Over Recommended Operating Conditions
Description
3-27
DC and Switching Characteristics
LatticeECP2 Family Data Sheet
Min.
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
420
420
420
—
—
—
—
—
ps p-p
ps p-p
cycles
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ns
ps
ns
ns
%
%
%