LCMXO2-1200HC-4TG144C Lattice, LCMXO2-1200HC-4TG144C Datasheet - Page 29

• Manufacturer Part Number: LCMXO2-1200HC-4TG144C
• Description: FPGA - Field Programmable Gate Array 1280 LUTs 108 I/O 3.3V -4 SPD
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-4TG144C

• Rohs: yes
• Number Of Gates: 1.2 K
• Embedded Block Ram - Ebr: 64 Kbit
• Number Of I/os: 108
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Distributed Ram: 10 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 3.49 mA
• Factory Pack Quantity: 60
• User Flash Memory - Ufm: 64 Kbit

Table 2-13. Supported Output Standards
sysIO Buffer Banks
The numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher
density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side).
The MachXO2-1200 and lower density devices have four banks (one bank per side). Figures 2-18 and 2-19 show
the sysIO banks and their associated supplies for all devices.
Single-Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
SSTL25 (Class I)
SSTL18 (Class I)
HSTL18(Class I)
Differential Interfaces
LVDS
BLVDS, MLVDS, RSDS
LVPECL
Differential SSTL18
Differential SSTL25
Differential HSTL18
1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.
2. These interfaces can be emulated with external resistors in all devices.
1, 2
2
Output Standard
2
2-25
V
CCIO
2.5, 3.3
3.3
3.3
2.5
1.8
1.5
1.2
3.3
2.5
1.8
1.8
2.5
3.3
1.8
2.5
1.8
—
—
—
—
—
(Typ.)
MachXO2 Family Data Sheet
Architecture