LCMXO2-256HC-6SG32C Lattice, LCMXO2-256HC-6SG32C Datasheet - Page 2
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO2-256HC-6SG32C
Manufacturer Part Number
LCMXO2-256HC-6SG32C
Description
FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 3.3V -6 Speed
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-256HC-6SG32C
Rohs
yes
Number Of Gates
256
Number Of Logic Blocks
32
Embedded Block Ram - Ebr
0 Kbit
Number Of I/os
22
Maximum Operating Frequency
388 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Distributed Ram
2 Kbit
Operating Supply Current
1.15 mA
Factory Pack Quantity
490
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
January 2013
Features
Flexible Logic Architecture
Ultra Low Power Devices
Embedded and Distributed Memory
On-Chip User Flash Memory
Pre-Engineered Source Synchronous I/O
High Performance, Flexible I/O Buffer
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
• Six devices with 256 to 6864 LUT4s and
• Advanced 65 nm low power process
• As low as 19 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
• Up to 240 Kbits sysMEM™ Embedded Block
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I
• Can be used as soft processor PROM or as
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with
• Programmable sysIO™ buffer supports wide
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
19 to 335 I/Os
RAM
JTAG interfaces
Flash memory
DQS support
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
2
C and
MachXO2 Family Data Sheet
1-1
Flexible On-Chip Clocking
Non-volatile, Infinitely Reconfigurable
TransFR™ Reconfiguration
Enhanced System Level Support
Broad Range of Package Options
• Eight primary clocks
• Up to two edge clocks for high-speed I/O
• Up to two analog PLLs per device with
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I
• Supports background programming of non-vola-
• Optional dual boot with external SPI memory
• In-field logic update while system operates
• On-chip hardened functions: SPI, I
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
• Small footprint package options
• Density migration supported
• Advanced halogen-free packaging
interfaces (top and bottom sides only)
fractional-n frequency synthesis
tile memory
counter
range
fpBGA, QFN package options
– Wide input frequency range (10 MHz to
– As small as 2.5x2.5mm
400 MHz)
Introduction
DS1035
Data Sheet DS1035
Introduction_01.6
2
C, timer/
2
C