ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 96

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

G.1.2. WIP Status Bit [0]
G.1.3. WEN Status Bit [1]
G.1.4. WAKEb Status Bit [2]
G.1.5. CRCE Status Bit [4]
G.1.6. RRDY Status Bit [6]
G.1.7. EERR Status Bit [7]
The WIP status bit is used to indicate the device is busy or a "Write is In Progress". If WIP = 0b, then the ATAES132 is in the
active state and is waiting to receive a command. If WIP = 1b, then ATAES132 is in the active state and is performing an
EEPROM write, or is processing an ATAES132 command.
If the ATAES132 is configured in I
information).
If the ATAES132 is configured in SPI interface mode, then the WEN status bit is 0b after the device initially powers up or exits
the sleep state (See Appendix K for SPI interface information). When WEN = 0b the user memory is write protected, and any
attempt to write the user memory using the SPI WRITE command will fail. The host must send an SPI WREN command to the
device to set WEN = 1b prior to each SPI WRITE command.
If the ATAES132 is configured in SPI interface mode, then the WEN status bit will return to 0b when any write instruction is
received. The WEN status bit can be forced to 0b by sending a SPI WRDI command (See Section K.3.3), or by sending a
RESET command (See Section 7.23), or by putting the device in the sleep state. Powering the device off will reset the WEN
bit to 0b. The SPI READ command and SPI RDSR command do not affect the state of the WEN bit.
It is not necessary to set WEN = 1b prior to writing to the command memory buffer or the IO address reset register (See
Appendix D). Writing the command memory buffer or the IO address reset register forces WEN to 0b.
The WAKEb status bit is 0b when the ATAES132 has completed a power up sequence and is in the ACTIVE state. WAKEb is
1b when the ATAES132 is in the sleep or standby state, or is in the process of waking up.
Note:
The CRCE status bit is set to 1b if a block is received with a short count, bad checksum, or if the block causes a buffer
overrun. If only the checksum (CRC) was incorrect, then the block may be resent without change. If the command memory
buffer contains a partial command block, then the CRCE status bit is 1b and all other status bits are 0b. This indicates that the
correct checksum has not yet been received.
The EERR bit will remain 0b when a checksum error occurs and the response memory buffer will remain empty because these
errors do not result in a ReturnCode being generated. If a buffer overrun occurs, then the CRCE and EERR bits will be set to
1b.
The RRDY status bit is 0b when the response memory buffer is empty. If RRDY = 1b, then the response memory buffer
contains a response block or a ReturnCode resulting from the most recent command or command block received (See Section
D.3 for response memory buffer information).
If the command is processed without error, the EERR bit is set to 0b. When any error other than a checksum error occurs, the
EERR status bit is set to 1b to indicate an error. The host can read the error code (ReturnCode) from the response memory
buffer (address 0xFE00) using the READ command if the RRDY status bit is 1b.
Reading the STATUS register does not reset the status register bits or alter the response memory buffer contents. Reading
the response memory buffer does not alter the contents of the response memory buffer or the STATUS register. Reading
beyond the end of the response memory buffer will not cause the STATUS register bits to change.
Reading the STATUS register will cause a device in the sleep state or standby state to wakeup. (See Appendix
L for power state and power management information.)
2
C interface mode, then the WEN status bit is always 0b (See Appendix J for I
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
2
C
96