ATAES132-SH-ER Atmel, ATAES132-SH-ER Datasheet - Page 155

• Manufacturer Part Number: ATAES132-SH-ER
• Description: EEPROM AES 32Kbit EE I2C
• Manufacturer: Atmel

Specifications of ATAES132-SH-ER

• Rohs: yes
• Maximum Clock Frequency: 1 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: I2C
• Factory Pack Quantity: 2300

P.2.3. HOLD
P.2.4. Page Write Operations
P.2.5. Read Operations
P.2.6. Read Protect
P.2.7. STATUS Register
The AT25320B
low), and then resume the communication sequence (by bringing
point where it was paused, as if there was no interruption.
The ATAES132 does not have a HOLD function. If communications are interrupted, the sequence must be restarted,
beginning with a high to low transition on the
If the host attempts to write data across the physical (32 byte) EEPROM page boundary, the AT25320B wraps to the
beginning of the EEPROM page where the page write operation begin and performs the EEPROM write after receiving a low
to high transition on the
AT25320B wraps the data at the page boundary and performs the EEPROM write after receiving a STOP condition. Partial
page writes are supported by the AT25320B.
The ATAES132 does not allow write operations to cross physical (32 byte) EEPROM page boundaries (see Section B.2), and
does not allow a write operation if more than 32 data bytes are received from the host. In both cases, the EEPROM contents
remain unchanged, the data is discarded, and an error bit is set in the STATUS register (see Section J.3.3). Partial page
writes are supported by the ATAES132.
Reading beyond the end of physical memory on AT25320B causes the internal data address register to rollover to address
zero. The read operation continues from address zero.
If an ATAES132 read operation begins at a valid user memory address but continues past the end of user memory, the read
operation will not wrap to the beginning of user memory. Reading beyond the end of user memory causes 0xFF to be
returned to the host in reply to the read, the internal data address register stops incrementing, and an error bit is set in the
STATUS register.
The Atmel AT25320B and other standard SPI EEPROM do not have a read inhibit function.
On the ATAES132, the user memory read permissions are controlled by the ZoneConfig Registers (see Section E.2.22). The
user memory is divided into 16 user zones which are independently controlled by 16 ZoneConfig Registers – different read
permissions can be assigned to different sections of the memory. If read access is prohibited, then 0xFF will be returned to
the host in reply to a read command (see Section 5.2). By default all user memory has open read access.
The AT25320B STATUS register definition is shown in Table P-1. The default state of all STATUS bits is 0b. The WPEN bit
controls the write protect pin. Block write protection is controlled by the BP0 and BP1 bits. If WEN = 1b, then the device is
write enabled. If WIP = 0b, the device is ready to accept a command – WIP = 1b indicates a write cycle is in progress. The
Reserved bits are 0b except when an internal write cycle is in progress. All bits of the STATUS register are 1b when an
internal write cycle is in progress.
Table P-49. Atmel AT25320B STATUS register fefinition
WPEN
Bit 7
Reserved
Bit 6
input pin allows the host to pause communication with the memory temporarily (by bringing
input. If the host attempts to write more than 32 bytes in a page write operation, then the
Reserved
Bit 5
Reserved
Bit 4
input.
Bit 3
BP1
Atmel ATAES132 Preliminary Datasheet
high). The sequence continues exactly from the
Bit 2
BP0
WEN
Bit 1
8760A−CRYPTO−5/11
Bit 0
WIP
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