M95320-DRMN6TP STMicroelectronics, M95320-DRMN6TP Datasheet - Page 17
M95320-DRMN6TP
Manufacturer Part Number
M95320-DRMN6TP
Description
EEPROM 32Kb SPI bus EEPROM 20 MHz 4kB
Manufacturer
STMicroelectronics
Datasheet
1.M95320-RMC6TG.pdf
(46 pages)
Specifications of M95320-DRMN6TP
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M95320-W M95320-R M95320-DF
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7.
Figure
Write Enable (WREN) sequence
S
C
D
Q
7, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 5711 Rev 15
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI02281E
Instructions
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