M95128-DFMN6TP STMicroelectronics, M95128-DFMN6TP Datasheet - Page 21

• Manufacturer Part Number: M95128-DFMN6TP
• Description: EEPROM Automotive 128kBit SPI High Speed Clock
• Manufacturer: STMicroelectronics

Specifications of M95128-DFMN6TP

• Rohs: yes

M95128-W M95128-R M95128-DF
Table 7.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
●
●
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●
●
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
signal
W
1
0
1
0
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
either setting the SRWD bit after driving the Write Protect (W) input pin low,
or driving the Write Protect (W) input pin low after setting the SRWD bit.
SRWD
bit
0
0
1
1
Protection modes
Hardware-
Software-
protected
protected
(HPM)
(SPM)
Mode
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Write protection of the
Doc ID 5798 Rev 16
Status Register
Write-protected
Write-protected
Protected area
Table
7.
Memory content
(1)
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
Table
Instructions
2.
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