M95256-DFCS6TP/K STMicroelectronics, M95256-DFCS6TP/K Datasheet - Page 29

• Manufacturer Part Number: M95256-DFCS6TP/K
• Description: EEPROM 256Kb serial SPI bus 20 MHz 5ms 64 Byte
• Manufacturer: STMicroelectronics

Specifications of M95256-DFCS6TP/K

• Rohs: yes

M95256-W M95256-R M95256-DR M95256-DF
6.10
Lock ID (available only in M95256-D devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is t
parameters). The instruction sequence is shown in
The instruction is discarded, and is not executed, under the following conditions:
●
●
●
Figure 18. Lock ID sequence
If a Write cycle is already in progress,
If the Block Protect bits (BP1,BP0) = (1,1),
If a rising edge on Chip Select (S) happens outside of a byte boundary.
W
(as specified in AC characteristics in
Doc ID 12276 Rev 19
Figure
18.
Section 9: DC and AC
Instructions
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