M24C64-FMC6TG STMicroelectronics, M24C64-FMC6TG Datasheet - Page 14

• Manufacturer Part Number: M24C64-FMC6TG
• Description: EEPROM 65 Kbit Serial I2C 1.7V to 5.5V EEPROM
• Manufacturer: STMicroelectronics

Specifications of M24C64-FMC6TG

• Product Category: EEPROM
• Rohs: yes

Instructions
5
5.1
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Instructions
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3.
Table 4.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
cycle t
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in
A15
A7
W
th
is triggered. A Stop condition at any other time slot does not trigger the internal
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
Most significant address byte
Least significant address byte
A14
A6
A13
A5
Doc ID 16891 Rev 27
A12
A4
M24C64-W M24C64-R M24C64-F M24C64-DF
A11
A3
Figure
A10
8, and waits for two address
A2
Figure
9.
A9
A1
W
), the
A0
A8