M24C64-FMC6TG STMicroelectronics, M24C64-FMC6TG Datasheet - Page 13

• Manufacturer Part Number: M24C64-FMC6TG
• Description: EEPROM 65 Kbit Serial I2C 1.7V to 5.5V EEPROM
• Manufacturer: STMicroelectronics

Specifications of M24C64-FMC6TG

• Product Category: EEPROM
• Rohs: yes

M24C64-W M24C64-R M24C64-F M24C64-DF
4.5
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
Table 2.
1. The most significant bit, b7, is sent first.
2.
3. For the 5-bump WLCSP package, (E0,E1,E2) inputs are internally connected to (0,0,1)
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
The 8
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
Device select code
when addressing the
memory array
Device select code
when accessing the
Identification page
Table
E0, E1 and E2 are compared with the value read on input pins E0,E1,and E2.
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
2(on Serial Data (SDA), most significant bit first).
Device select code
b7
1
1
Device type identifier
Doc ID 16891 Rev 27
b6
0
0
b5
1
1
(1)
th
b4
0
1
bit time. If the device does not match
Chip Enable address
b3
E2
E2
E1
E1
b2
Device operation
b1
E0
E0
(2)(3)
RW
RW
RW
b0
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