AT24C512C-SSHMEU-T Atmel, AT24C512C-SSHMEU-T Datasheet - Page 3

• Manufacturer Part Number: AT24C512C-SSHMEU-T
• Description: EEPROM SERIAL EEPROM 512K (64KX8) 2-WIRE 1.7V
• Manufacturer: Atmel

Specifications of AT24C512C-SSHMEU-T

• Rohs: yes
• Memory Size: 512 KB
• Organization: 65536 x 8
• Maximum Clock Frequency: 1000 KHz
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: 2-Wire
• Minimum Operating Temperature: - 40 C
• Operating Current: 2 mA
• Factory Pack Quantity: 100
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.7 V

3.
4.
Block Diagram
Pin Descriptions
Serial Clock (SCL) — The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge
clock data out of each device.
Serial Data (SDA) — The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven, and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A
connected for compatibility with other Atmel AT24Cxx devices. When the pins are hardwired, as many as eight 512K
devices may be addressed on a single bus system (see
these pins are left floating, the A
coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a
known state. When using a pull-up resistor, Atmel recommends using 10k or less.
Write Protect (WP) — The Write Protect input, when connected to GND, allows normal write operations. When WP pin
is connected directly to V
internally pulled down to GND; however, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pin to a known state. When using a pull-up resistor, Atmel recommends using
10k or less.
Table 4-1.
GND
SDA
SCL
WP
V
A
A
A
CC
2
1
0
WP Pin
At GND
Status
At V
CC
Write Protect
D
IN
2
Comparator
, A
Logic
Start
Stop
Address
CC
Device
1
Normal Read/Write Operations
, A
, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
Part of the Array Protected
LOAD
D
0
OUT
R/W
) — The A
Atmel AT24C512C
2
, A
1
Full Array
, and A
Addr/counter
Data Word
2
COMP
, A
0
LOAD
1
pins will be internally pulled down to GND. However, due to capacitive
, and A
Y DEC
Control
Serial
Logic
INC
0
pins are device address inputs that are hardwired or left not
Section 7. “Device Addressing” on page 9
EN
H.V. Pump/Timing
Data Recovery
Serial MUX
EEPROM
D
OUT
Logic
/ACK
Atmel AT24C512C [DATASHEET]
8720C–SEEPR–7/12
for more details). If
3