CAV24C64YE-GT3 ON Semiconductor, CAV24C64YE-GT3 Datasheet - Page 3

• Manufacturer Part Number: CAV24C64YE-GT3
• Description: EEPROM 64KB I2C SER EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAV24C64YE-GT3

• Product Category: EEPROM
• Rohs: yes
• Memory Size: 64 Kbit
• Organization: 8 K x 8
• Data Retention: 100 Years
• Maximum Clock Frequency: 0.1 MHz
• Maximum Operating Current: 2 mA
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TSSOP-8
• Access Time: 3500 ns
• Interface Type: IC2
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.5 V

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
Table 4. PIN IMPEDANCE CHARACTERISTICS
Table 6. A.C. TEST CONDITIONS
Table 5. A.C. CHARACTERISTICS
t
PU
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
C
C
I
and JEDEC test methods.
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
WP
I
t
T
PU
A
F
IN
IN
Symbol
Symbol
i
(Notes 7, 8)
t
t
t
t
t
t
t
HD:DAT
SU:STO
HD:STA
SU:STA
SU:DAT
(Note 6)
(Note 6)
(Note 5)
SU:WP
HD:WP
t
F
t
(Note 4)
(Note 4)
t
is the delay between the time V
(Note 5)
HIGH
t
LOW
BUF
t
t
WR
SCL
DH
t
AA
R
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Address Input Current
(A0, A1, A2)
Product Rev F
Parameter
CC
is stable and the device is ready to accept commands.
0.2 x V
≤ 50 ns
0.3 x V
0.5 x V
Current Source: I
(V
CC
Parameter
= 2.5 V to 5.5 V, T
CC
CC
CC
, 0.7 x V
to 0.8 x V
(V
http://onsemi.com
OL
CC
V
V
V
V
V
V
V
V
V
V
CC
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
CC
= 3 mA; C
= 2.5 V to 5.5 V, T
> V
< V
= 0 V, T
= 0 V, T
< V
< V
< V
< V
< V
> V
A
IH
IH
IH
IH
IH
IH
IH
IH
= −40°C to +125°C, unless otherwise specified.) (Note 6)
, V
, V
, V
, V
, V
, V
3
A
A
CC
CC
CC
CC
CC
CC
L
= 25°C
= 25°C
= 100 pF
= 5.5 V
= 5.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
Conditions
CC
A
), the strong pull−down reverts to a weak current source.
= −40°C to +125°C, unless otherwise specified.)
Min
250
100
4.7
4.7
4.7
2.5
4
4
0
4
0
Standard
1000
Max
100
300
100
3.5
5
1
Min
100
100
0.6
1.3
0.6
0.6
0.6
1.3
2.5
0
0
Fast
Max
130
120
80
50
35
25
8
6
2
2
Max
400
300
300
100
0.9
5
1
Units
Units
kHz
pF
pF
mA
mA
ms
ms
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms