DS28E05P+T Maxim Integrated, DS28E05P+T Datasheet - Page 3

• Manufacturer Part Number: DS28E05P+T
• Description: EEPROM 1W 1KB FTP MEMORY TSOC
• Manufacturer: Maxim Integrated

Specifications of DS28E05P+T

• Rohs: yes
• Memory Size: 1 KB
• Organization: 7 Pages x 16
• Data Retention: 10 yr
• Maximum Operating Current: 20 uA
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOC-6
• Interface Type: 1-Wire
• Minimum Operating Temperature: - 40 C
• Operating Current: 20 uA
• Supply Voltage - Max: + 4 V
• Supply Voltage - Min: - 0.5 V
• Part # Aliases: 90-2805V+000

DS28E05
Electrical Characteristics (continued)
(T
Note 1: Limits are 100% production tested at T
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
Note 4: Typical value represents the internal parasite capacitance when V
Note 5: Guaranteed by design and/or characterization only. Not production tested.
Note 6: V
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to V
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: Defines maximum possible bit rate. Equal to 1/(t
Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15: Interval after t
Note 16: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V
Note 17: δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V
Note 18: Current drawn from IO during the EEPROM programming interval, during which the voltage at IO must not drop below 1.8V.
Note 19: The t
Note 20: Write-cycle endurance is tested in compliance with JESD47G.
Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22: Data retention is tested in compliance with JESD47G.
Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
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A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
charged, it does not affect normal communication.
capacitive loading on IO. Lower V
V
ence detect pulse could be outside this interval but will be complete within 2ms after power-up.
maximum duration for the master to pull the line low is t
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
This condition is met with R
valid Write Memory sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from I
data sheet limit at operating temperature range is established by reliability testing.
peratures is not recommended.
TL
TL
, V
, V
PROG
TH
TH
TH
, and V
, and V
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte for a
RSTL
HY
HY
are a function of the internal supply voltage, which is a function of V
.
during which a bus master can read a logic 0 on IO if there is a DS28E05 present. The power-up pres-
PUPMAX
PUP
over the entire V
, higher R
A
= +25°C and/or T
PUP
PROG
W0LMIN
ILMAX
, shorter t
PUP
to I
W1LMAX
+ t
at all times the master is driving IO to a logic 0 level.
L
A
range.
.
RECMIN
= +85°C. Limits over the operating temperature range and rel-
REC
+ t
, and heavier capacitive loading all lead to lower values of
PUP
).
F
- ε and t
is first applied. Once the parasite capacitance is
W0LMAX
+ t
PUP
F
HY
- ε, respectively.
, R
to be detected as logic 0.
PUP
RLMAX
1-Wire EEPROM
, 1-Wire timing, and
IL
IL
to V
+ t
to the input-high
Maxim Integrated │ 3
F
TH
.
. The actual