M95256-DFDW6TP STMicroelectronics, M95256-DFDW6TP Datasheet - Page 19

• Manufacturer Part Number: M95256-DFDW6TP
• Description: EEPROM 256-Kbit serial SPI bus EEPROM
• Manufacturer: STMicroelectronics

Specifications of M95256-DFDW6TP

• Rohs: yes
• Memory Size: 256 Kbit
• Organization: 32768 x 8 bit
• Data Retention: 200 yr
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Current: 5 mA
• Operating Supply Voltage: 1.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 1.7 V

M95256-W M95256-R M95256-DR M95256-DF
6.3
6.3.1
6.3.2
6.3.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in
Figure 10. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
●
●
●
●
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
S
C
D
Q
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
0
High Impedance
1
2
Instruction
3
4
5
Doc ID 12276 Rev 19
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
Table
3
2
2) becomes protected against Write
Figure
1
0
MSB
7
10.
6
Status Register Out
5
4
3
2
1
Instructions
0
7
AI02031E
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