AT24MAC402-SSHM-T Atmel, AT24MAC402-SSHM-T Datasheet - Page 11

• Manufacturer Part Number: AT24MAC402-SSHM-T
• Description: EEPROM 2-Kbit Serial EEPROM
• Manufacturer: Atmel

Specifications of AT24MAC402-SSHM-T

• Rohs: yes
• Memory Size: 2 Kbit
• Organization: 256 B x 8
• Data Retention: 100 yr
• Maximum Clock Frequency: 1000 KHz
• Maximum Operating Current: 6 uA
• Operating Supply Voltage: 1.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8

6.
7.
Table 5-1.
Write Operations
Byte Write: A Byte Write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again acknowledge or respond with a zero and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the
addressing device, such as a microcontroller, must terminate the write sequence with a Stop condition. At this time, the
EEPROM enters an internally-timed write cycle, t
cycle and the EEPROM will not respond until the write is complete (see
acknowledge a write command, but not write the data if the software or hardware write protection has been enabled. The
write cycle time must be observed even when the write protection is enabled.
Page Write: The AT24MAC402/602 is capable of a 16-byte Page Write. A Page Write is initiated by the same method as
a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after
the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words.
The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write
sequence with a Stop condition (see
The lower four data word address bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the internally generated word
address reaches the page boundary, the next byte is placed at the beginning of the same page. If more than sixteen data
words are transmitted to the EEPROM, the data word address will roll-over and previous data will be overwritten. The
address roll-over during write is from the last byte of the current page to the first byte of the same page. The device will
acknowledge a write command, but will not write the data if the software or hardware write protection has been enabled.
The write cycle time must be observed even when the write protection is enabled.
Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.
Write Protection
Once enabled, the Software Write Protection write protects only the first-half of the array (00h - 7Fh) while the hardware
write protection, via the WP pin, is used to protect the entire array (see
Permanent Software Write Protection (PSWP): The Permanent Software Write Protection is enabled by sending a
command to the device, similar to a normal write command, which programs the Permanent Write Protect Register. This
must be done with the WP pin low. The Write Protect Register is programmed by sending a write command with the
device address of ‘0110’(6h) instead of ‘1010’ (Ah) with the address and data bit(s) being don’t cares (see
on page
the device will no longer acknowledge the ‘0110’ (6h) control byte and cannot be reversed even if the device is
powered down. The Permanent Software Write Protection can only be invoked on a SOT23 packaged device with the
A2, A1, and A0 bits set to zero.
Reversible Software Write Protection (RSWP): The Reversible Software Write Protection is enabled by sending a
command to the device, similar to a normal write command, which programs the Reversible Write Protect Register. This
must be done with the WP pin low. The Reversible Write Protect Register is programmed by sending a write command
‘01100010’(62h) with pins A
EEPROM
EUI or Serial Number Read
12). The write cycle time must be observed. Once the permanent software write protection has been enabled,
Device Address
Access Area
2
and A
Figure 8-2 on page
1
tied to ground or not connected and the A
Bit 7
1
1
WR
, to the nonvolatile memory. All inputs are disabled during this write
Atmel AT24MAC402/602 [PRELIMINARY DATASHEET]
Bit 6
17).
0
0
Bit 5
1
1
Table 7-1 on page
Figure 8-1 on page
Bit 4
0
1
0
pin connected to V
Bit 3
A
A
2
2
13).
16). The device will
Bit 2
A
A
1
1
8807B–SEEPR–9/2012
HV
Bit 1
(see
A
A
0
0
Figure 7-2
Figure 7-1
Bit 0
R/W
1
11