DAC1008D650HN/C1 NXP Semiconductors, DAC1008D650HN/C1 Datasheet - Page 18

• Manufacturer Part Number: DAC1008D650HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D650HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
DAC1008D650
Product data sheet
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges will reach each of the
DACs at different times.
The worst case clock skew is given by t
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by t = TDAC  t
Fig 9.
Clock skew case 1: Master is the farthest
slave 1 clock
slave 2 clock
master clock
All information provided in this document is subject to legal disclaimers.
ref clock
Rev. 3 — 31 January 2012
PH03
PH02
PH01
2, 4 or 8 interpolating DAC with JESD204A
1
= PH01  PH03, where PH0x represents the
TDAC
DAC1008D650
001aal072
© NXP B.V. 2012. All rights reserved.
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