74LVCH16245APAG8 IDT, 74LVCH16245APAG8 Datasheet - Page 5
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74LVCH16245APAG8
Manufacturer Part Number
74LVCH16245APAG8
Description
Bus Transceivers 16-bit Bus Transceiv er w/3-State Outputs
Manufacturer
IDT
Datasheet
1.74LVCH16245APAG8.pdf
(6 pages)
Specifications of 74LVCH16245APAG8
Rohs
yes
Part # Aliases
IDT74LVCH16245APAG8
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
SWITCH POSITION
NOTES:
1.
2.
DEFINITIONS:
C
R
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
L
T
Symbol
Generator
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
V
V
For t
For t
LOAD
V
V
C
Pulse
HZ
LZ
IH
T
L
OUTPUT 2
OUTPUT 1
SK
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
Disable High
INPUT
(1, 2)
Disable Low
Enable High
Enable Low
Open Drain
V
CC
Test
(1)
= 3.3V±0.3V V
V
300
300
2.7
1.5
50
6
IN
Test Circuit for All Outputs
t
SK
(x)
Output Skew - t
R
= t
T
t
D.U.T.
PLH1
V
PLH2
CC
CC
t
PLH2
(1)
300
300
2.7
1.5
50
6
= 2.7V
-
t
SK
t
PLH1
V
(x)
OUT
OUT
SK
F
F
or
(
≤ 2ns; t
≤ 2.5ns; t
t
X
V
PHL1
of the Pulse Generator.
)
CC
t
C
PHL2
t
PHL2
(2)
L
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
R
V
GND
Open
t
Vcc
150
150
LOAD
SK
-
30
R
≤ 2ns.
t
PHL1
500Ω
≤ 2.5ns.
500Ω
(x)
LVC Link
LVC Link
0V
V
V
V
V
V
V
V
V
T
T
T
IH
OL
OL
OH
OH
GND
V
Open
Unit
mV
mV
pF
V
V
V
LOAD
5
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
HIGH-LOW-HIGH
CONTROL
CONTROL
LOW-HIGH-LOW
CONTROL
SAME PHASE
OUTPUT
OUTPUT
TIMING
INPUT
INPUT
DATA
INPUT
HIGH
OUTPUT
LOW
Set-up, Hold, and Release Times
PULSE
PULSE
Enable and Disable Times
CLOSED
SWITCH
SWITCH
Propagation Delay
ENABLE
OPEN
Pulse Width
t
t
PZH
PZL
t
INDUSTRIAL TEMPERATURE RANGE
t
PLH
PLH
t
SU
t
SU
V
0V
V
V
T
T
LOAD/2
t
W
t
REM
t
H
t
PHZ
t
t
DISABLE
PHL
PHL
t
H
t
PLZ
LVC Link
LVC Link
V
LVC Link
V
T
T
LVC Link
V
V
0V
V
V
V
V
V
0V
0V
V
V
V
V
V
V
0V
OH
V
IH
T
T
OL
IH
T
T
IH
OH
LOAD/2
LZ
OL
HZ
0V
0V
0V
0V
V
V
V
V
V
V
V
V
T
T
T
T
IH
IH
IH
IH