74LVCH1T45GS,132 NXP Semiconductors, 74LVCH1T45GS,132 Datasheet
74LVCH1T45GS,132
Specifications of 74LVCH1T45GS,132
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74LVCH1T45GS,132 Summary of contents
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Dual supply translating transceiver; 3-state Rev. 6 — 6 August 2012 1. General description The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A ...
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... NXP Semiconductors Latch-up performance exceeds 100 mA per JESD 78 Class II 24 mA output drive (V Inputs accept voltages up to 5.5 V Low power consumption: 16 A maximum I I OFF Multiple package options Specified from 40 C to +85 C and 40 C to +125 C ...
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... NXP Semiconductors 5. Functional diagram 5 DIR CC(A) Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC1T45 74LVCH1T45 CC(A) CC(B) GND 2 5 DIR 001aaj991 Fig 3. Pin configuration SOT363 (SC-88) 6.2 Pin description Table 3. Pin description Symbol Pin V 1 CC(A) GND DIR CC(B) 74LVC_LVCH1T45 Product data sheet 74LVC1T45 ...
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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Supply voltage Input DIR CC(A) CC( [3] GND X [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. [2] The input circuit of the data I/O is always active. [3] When either GND level, the device goes into suspend mode. ...
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... NXP Semiconductors Table 6. Recommended operating conditions Symbol Parameter V output voltage O T ambient temperature amb t/V input transition rise and fall rate [ the supply voltage associated with the output port. CCO [ the supply voltage associated with the input port. ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level data input IH input voltage V CCI V CCI V CCI V CCI V CCI DIR input V CCI V CCI V CCI V CCI V CCI V LOW-level data input IL input voltage V CCI V CCI ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 100 CCO input leakage DIR input ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I power-off A port; V OFF leakage V CC(A) current V CC(B) B port CC(B) V CC(A) I supply current A port CC(A) V CC(A) V CC(A) V CC(A) B port CC(A) V CC(A) V CC(B) V CC(B) A plus B port ( ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay t HIGH to OFF-state PHZ propagation delay t LOW to OFF-state PLZ propagation delay ...
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... NXP Semiconductors Table 11. Typical power dissipation capacitance at V Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C power dissipation A port: (direction A to B); PD capacitance B port: (direction port: (direction B to A); B port: (direction [ used to determine the dynamic power dissipation (P PD ...
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... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +85 C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to HIGH DIR to A PZH propagation delay DIR OFF-state to LOW DIR to A PZL propagation delay ...
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... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +85 C Table 12. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t LOW to OFF-state DIR to A PLZ propagation delay DIR OFF-state to HIGH DIR to A PZH propagation delay ...
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... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +125 C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to LOW DIR to A PZL propagation delay DIR 2 2.7 V CC(A) t LOW to HIGH PLH propagation delay ...
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... NXP Semiconductors Dynamic characteristics for temperature range 40 C to +125 C Table 13. Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t OFF-state to HIGH DIR to A PZH propagation delay DIR OFF-state to LOW DIR to A PZL propagation delay ...
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... NXP Semiconductors Table 14. Measurement points Supply voltage Input CC(A) CC( 1.6 V 0.5V 1. 2.7 V 0.5V 3 5.5 V 0.5V [ the supply voltage associated with the data input port. CCI [ the supply voltage associated with the output port. CCO Test data is given in Table R = Load resistance. ...
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... NXP Semiconductors 13. Typical propagation delay characteristics 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( ...
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... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 10. Typical propagation delay vs load capacitance; T ...
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... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 11. Typical propagation delay vs load capacitance; T ...
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... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 12. Typical propagation delay vs load capacitance; T ...
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... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 13. Typical propagation delay vs load capacitance; T ...
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... NXP Semiconductors 14 t PHL (ns HIGH to LOW propagation delay ( PHL (ns HIGH to LOW propagation delay ( ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( 1.8 V. CC(B) ( 2.5 V. CC(B) ( 3.3 V. CC(B) ( 5.0 V. CC(B) Fig 14. Typical propagation delay vs load capacitance; T ...
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... NXP Semiconductors 14. Application information 14.1 Unidirectional logic level-shifting application The circuit given unidirectional logic level-shifting application. Fig 15. Unidirectional logic level-shifting application Table 16. Pin 74LVC_LVCH1T45 Product data sheet 74LVC1T45; 74LVCH1T45 Figure example of the 74LVC1T45; 74LVCH1T45 being used V CC1 ...
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... NXP Semiconductors 14.2 Bidirectional logic level-shifting application Figure 16 level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. V I/O-1 DIR CTRL Fig 16. Bidirectional logic level-shifting application Table 17 system-2 and then from system-2 to system-1 ...
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... NXP Semiconductors 14.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. V CC( 1.8 V 2.5 V 3.3 V 5.0 V 14.4 Enable times Calculate the enable times for the 74LVC1T45; 74LVCH1T45 using the following formulas: • t PZH • ...
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... NXP Semiconductors 15. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 17. Package outline SOT363 (SC-88) 74LVC_LVCH1T45 Product data sheet 74LVC1T45; 74LVCH1T45 ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.5 0.04 0.25 1.50 mm nom 0.20 1.45 min 0.17 1.40 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 19. Package outline SOT891 (XSON6) ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1115 Fig 20. Package outline SOT1115 (XSON6) ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1202 Fig 21. Package outline SOT1202 (XSON6) ...
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... NXP Semiconductors 16. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model 17. Revision history Table 20. Revision history Document ID Release date 74LVC_LVCH1T45 v.6 20120806 • Modifications: Package outline drawing of SOT886 74LVC_LVCH1T45 v.5 20111219 • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13 Typical propagation delay characteristics ...