MPC8308ZQAFDA Freescale Semiconductor, MPC8308ZQAFDA Datasheet - Page 9
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MPC8308ZQAFDA
Manufacturer Part Number
MPC8308ZQAFDA
Description
Microprocessors - MPU E300 MP Pb 333
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8308VMAGDA.pdf
(83 pages)
Specifications of MPC8308ZQAFDA
Processor Series
MPC8308
Core
e300
Maximum Clock Frequency
333 MHz
Interface Type
I2C, JTAG, UART
Operating Supply Voltage
0.95 V to 1.05 V
Maximum Operating Temperature
0 C to + 105 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-473
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5.2
This table provides the reset initialization AC timing specifications.
This table provides the PLL lock times.
Freescale Semiconductor
Required assertion time of HRESET (input) to activate reset flow
Required assertion time of PORESET with stable power and clock applied to
SYS_CLK_IN
HRESET assertion (output)
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with
respect to negation of PORESET
Input hold time for POR configuration signals with respect to negation of HRESET
Time for the device to turn off POR configuration signal drivers with respect to the
assertion of HRESET
Time for the device to turn on POR configuration signal drivers with respect to the
negation of HRESET
Notes:
1. t
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].
SYS_CLK_IN
RESET AC Electrical Characteristics
System PLL lock time
e300 core PLL lock time
is the clock period of the input clock applied to SYS_CLK_IN.
Parameter/Condition
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Parameter/Condition
Table 11. RESET Initialization Timing Specifications
Table 12. PLL Lock Times
Min
—
—
Max
100
100
Min
512
32
32
—
4
0
1
Unit
s
s
Max
—
—
—
—
—
—
4
t
t
t
t
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
Note
—
—
RESET Initialization
Unit
ns
ns
ns
Notes
1, 2
—
—
—
1
1
2
9
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