MK21FN1M0VLQ10 Freescale Semiconductor, MK21FN1M0VLQ10 Datasheet - Page 5

• Manufacturer Part Number: MK21FN1M0VLQ10
• Description: ARM Microcontrollers - MCU K20_1MB
• Manufacturer: Freescale Semiconductor

Specifications of MK21FN1M0VLQ10

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: MK21FN1
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 1 MB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• Interface Type: CAN, I2C, I2S, SPI, UART, USB
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

freescale.com/ARM
Operating Temp: -40 °C to +105 °C
Internal Memory Security/Protection
Low-Power Touch Sense Interface
Modes, Clock Gating, 1.71–3.6 V
ARM
Kinetis L Series MCU Families
Multiple Low-Power Operation
(High Reliability, Fast Access)
ARM
90 nm TFS Flash Memory
High-Speed Comparators
Common Features
DMA, Cross Bar Switch
Analog Peripherals
Serial Interfaces
Low-Power Timers
LPUART, UART
Low-Power TPMs
®
®
System Timers
16-bit ADC
Cortex™-M0+ Core
ARM Cortex
12-bit DAC
Cortex
Memory
System
SPI, I
Timers
SRAM
RTC
Nested Vectored Interrupt Controller
Memory protection unit is not shown. This feature is not implemented on Kinetis L series.
2
AHB-Lite
Interface
C
[1]
[2]
™
-M0+ Core
[3]
Low Latency
I/O Interface
[1] Feature not available on all KL1, KL2, KL3 MCUs (some have 12-bit ADC)
[2] Feature not available on KL0 MCUs (KL0 MCUs have LPUART)
[3] CSP packages –40 °C to +85 °C
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
CPU
256 KB Flash
256 KB Flash
256 KB Flash
256 KB Flash
CPU
32 KB Flash
128 KB to
64 KB to
32 KB to
32 KB to
KL4 Family: USB, Segment LCD
8 KB to
KL1 Family: General Purpose
Internal Memory
KL3 Family: Segment LCD
Wake Up Interrupt Controller Interface
Micro Trace Buffer
KL0 Family: Entry Level
Data Watchpoint
Breakpoint
Optional Features
KL2 Family: USB
32 KB SRAM
32 KB SRAM
32 KB SRAM
32 KB SRAM
1 KB to 4 KB
16 KB to
8 KB to
4 KB to
4 KB to
SRAM
Communications
USB OTG (FS)
USB OTG (FS)
Access
Debug
Port
—
—
—
Segment
Segment
LCD
LCD
HMI
—
—
—
Energy Efficiency
• 1.77 CoreMark/MHz: 2x to 40x more
• More than 2x CoreMark/mA performance
• Single-cycle access to I/O and critical
• Two-stage pipeline: Reduced number of
• Excellent code density vs. 8-bit and 16-bit
• Optimized access to program memory:
Ease of Use
• 100 percent compatible with ARM Cortex-M0
• Simplified architecture: 56 instructions and
• Linear 4 GB address space: Removes the
• Micro trace buffer: Lightweight trace solution
• ARM third-party ecosystem support:
performance than 8- and 16-bit architectures,
nine percent more performance than ARM
Cortex-M0
than the closest 8- and 16-bit competitor
peripherals: Up to 50 percent faster than
standard I/O, improves reaction time to
external events allowing bit banding and
software protocol emulation
cycles per instruction (CPI), enabling faster
branch instruction and ISR entry
MCUs for reduced flash size, system cost
and power consumption
Accesses on alternate cycles for reduced
power consumption
and a subset ARM Cortex™-M3/M4: Reuse
existing compilers and debug tools
17 registers enables easy programming and
efficient packaging of 8/16/32-bit data in
memory
need for paging/banking, reducing software
complexity
allows fast bug identification and correction
Software and tools help minimize
development time/cost
Kinetis MCUs
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