LPC11U36FBD48/401, NXP Semiconductors, LPC11U36FBD48/401, Datasheet - Page 22

• Manufacturer Part Number: LPC11U36FBD48/401,
• Description: ARM Microcontrollers - MCU 32-bit ARM Cortex-M0 96KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11U36FBD48/401,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11U3x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 96 KB
• Data Ram Size: 10 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11U3X
Product data sheet
7.16.1 Features
7.15 System tick timer
7.16 Windowed WatchDog Timer (WWDT)
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
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Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time before watchdog
time-out.
Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
Incorrect feed sequence causes reset or interrupt, if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 1 — 20 April 2012
× 4.
cy(WDCLK)
× 256 × 4) to (T
32-bit ARM Cortex-M0 microcontroller
cy(WDCLK)
LPC11U3x
× 2
© NXP B.V. 2012. All rights reserved.
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× 4) in
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