MK40DN512VLQ10 Freescale Semiconductor, MK40DN512VLQ10 Datasheet - Page 63

• Manufacturer Part Number: MK40DN512VLQ10
• Description: ARM Microcontrollers - MCU KINETIS 512K USB LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK40DN512VLQ10

• Core: ARM Cortex M4
• Processor Series: K40
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

6.8.10 I
This section provides the AC timings for the I
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Freescale Semiconductor, Inc.
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Num
S10
S1
S2
S3
S4
S5
S6
S7
S8
S9
2
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
S switching specifications
Description
Table 46. I
S5
S7
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
S4
Figure 26. I
2
S master mode timing (limited voltage range)
S9
S9
S1
S3
S2
S10
2
S timing — master mode
S4
S2
2
S in master (clocks driven) and slave
S8
S7
Peripheral operating requirements and behaviors
2 x t
5 x t
45%
45%
Min.
-2.5
2.7
20
—
—
-3
0
SYS
SYS
Max.
55%
55%
3.6
15
15
—
—
—
—
—
MCLK period
S10
BCLK period
S6
S8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
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