MK40DN512VLQ10 Freescale Semiconductor, MK40DN512VLQ10 Datasheet - Page 61

• Manufacturer Part Number: MK40DN512VLQ10
• Description: ARM Microcontrollers - MCU KINETIS 512K USB LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK40DN512VLQ10

• Core: ARM Cortex M4
• Processor Series: K40
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

1. The master mode I
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I
6. C
6.8.8 UART switching specifications
See
Freescale Semiconductor, Inc.
SDA
SCL
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
= 1000 + 250 = 1250 ns (according to the Standard mode I
Pulse width of spikes that must be
Bus free time between STOP and
Fall time of SDA and SCL signals
Set-up time for STOP condition
b
t
f
General switching
suppressed by the input filter
= total capacitance of the one bus line in pF.
Figure 24. Timing definition for fast and standard mode devices on the I
S
START condition
Characteristic
t
HD; STA
t
LOW
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
t
r
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
t
HD; DAT
specifications.
t
Table 44. I
SU; DAT
t
HIGH
t
Symbol
SU
t
; STO
t
BUF
SP
t
f
t
f
2
C timing (continued)
t
SU; STA
Minimum
N/A
4.7
—
Standard Mode
2
4
C bus specification) before the SCL line is released.
SR
Maximum
Peripheral operating requirements and behaviors
300
N/A
—
—
t
HD; STA
20 +0.1C
Minimum
0.6
1.3
0
t
SP
t
Fast Mode
SU; STO
b
5
Maximum
SU; DAT
300
50
—
—
t
r
P
2
≥ 250 ns must
C bus
rmax
t


BUF
+ t
Unit
SU; DAT
ns
µs
µs
ns
S
61