MAX1179CEUI Maxim Integrated, MAX1179CEUI Datasheet - Page 8

• Manufacturer Part Number: MAX1179CEUI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1179CEUI

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 135 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 91 dB
• Interface Type: Parallel
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 1026 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
(AIN) charges capacitor C
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on C
resents a sample of the input. In hold mode, the capac-
itive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of a 16-bit resolution. Force CS low to put
valid data on the bus after conversion is complete.
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Figure 2. MAX1179/MAX1187/MAX1189 Timing Diagram
Figure 3. Typical Application Circuit for the MAX1179/MAX1187/
MAX1189
8
_______________________________________________________________________________________
ANALOG
INPUT
0.1µF
+5V ANALOG
R/C
CS
AIN
RESET
AV
DD
MAX1179
MAX1187
MAX1189
AGND DGND
HOLD
D0–D15
+5V DIGITAL
D0–D15
REFADJ
EOC
R/C
DV
CS
EOC
DD
REF
. The acquisition ends
Track and Hold (T/H)
HIGH-Z
µP DATA
BUS
0.1µF
t
t
DH
CSL
0.1µF
16-BIT
WIDE
t
ACQ
t
CSH
HOLD
10µF
DOWN CONTROL
t
DS
REF POWER-
rep-
t
CONV
Select standby mode or shutdown mode with R/C during
the second falling edge of CS (see Selecting Standby or
Shutdown Mode section). The MAX1179/MAX1187/
MAX1189 automatically enter either standby mode (ref-
erence and buffer on) or shutdown (reference and buffer
off) after each conversion depending on the status of
R/C during the second falling edge of CS.
The MAX1179/MAX1187/MAX1189 generate an internal
conversion clock to free the microprocessor from the bur-
den of running the SAR conversion clock. Total conver-
sion time after entering hold mode (second falling edge of
CS) to end-of-conversion (EOC) falling is 4.7µs (max).
CS and R/C control acquisition and conversion in the
MAX1179/MAX1187/MAX1189 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start (CS) is
ignored if R/C is high. The MAX1179/MAX1187/
MAX1189 need at least 12ms (C
= 10µF) for the internal reference to wake up and settle
before starting the conversion, if powering up from
shutdown. Reset the MAX1179/MAX1187/ MAX1189 by
toggling RESET with CS high. The next falling edge of
CS begins acquisition.
The MAX1179/MAX1187/MAX1189 have a selectable
standby or low-power shutdown mode. In standby
mode, the ADC’s internal reference and reference
buffer do not power down between conversions, elimi-
nating the need to wait for the reference to power up
before performing the next conversion. Shutdown mode
powers down the reference and reference buffer after
t
DV
t
DO
Selecting Standby or Shutdown Mode
DATA VALID
Applications Information
t
t
EOC
BR
HIGH-Z
Starting a Conversion
Power-Down Modes
REFADJ
Internal Clock
= 0.1µF, C
REF