CYUSB3012-BZXC Cypress Semiconductor, CYUSB3012-BZXC Datasheet - Page 7

• Manufacturer Part Number: CYUSB3012-BZXC
• Description: ARM Microcontrollers - MCU EZUSB SuperSpeedCtrl X32 256KB
• Manufacturer: Cypress Semiconductor

Specifications of CYUSB3012-BZXC

• Rohs: yes
• Core: ARM926EJ-S
• Processor Series: CYUSB301x
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 200 MHz
• Data Ram Size: 256 KB
• Operating Supply Voltage: 3.2 V to 6 V
• Package / Case: BGA-121
• Mounting Style: SMD/SMT
• Interface Type: I2C, I2S, SPI, UART, USB
• Number Of Timers: 1
• Supply Voltage - Max: 6 V
• Supply Voltage - Min: 3.2 V

JTAG Interface
FX3’s JTAG interface has a standard five-pin interface to connect
to a JTAG debugger in order to debug firmware through the
CPU-core's on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core
can be used for the FX3 application development.
Other Interfaces
FX3 supports the following serial peripherals:
■
■
■
■
The SPI, UART, and I
peripheral port.
The
Data Bus Width)
faces are multiplexed. Note that when GPIF II is configured for a
32-bit data bus width (CYUSB3012 and CYUSB3014), only the
UART interface is available on GPIO[53] to GPIO[56].
UART Interface
The UART interface of FX3 supports full-duplex communication.
It includes the signals noted in
Table 1. UART Interface Signals
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then FX3's UART only transmits data when the CTS
input is asserted. In addition to this, FX3's UART asserts the RTS
output signal, when it is ready to receive data.
Document Number: 001-52136 Rev. *L
UART
I
I
SPI
2
2
C
S
CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit
Signal
CTS
RTS
TX
RX
on page 13 shows details of how these inter-
2
S interfaces are multiplexed on the serial
Table
1.
Output signal
Description
Flow control
Flow control
Input signal
I
FX3’s I
Revision 3. This I
master; therefore, it may be used to communicate with other I
slave devices. For example, FX3 may boot from an EEPROM
connected to the I
FX3’s I
functionality.
The power supply for the I
separate power domain from the other serial peripherals. This
gives the I
voltage than the other serial interfaces.
The I
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I
feature to enable slower devices to exercise flow control.
The I
resistors. The pull-up resistors must be connected to VIO5.
I
FX3 has an I
FX3 functions as I
consists of four signals: clock line (I2S_CLK), serial data line
(I2S_SD), word select line (I2S_WS), and master system clock
(I2S_MCLK). FX3 can generate the system clock as an output
on I2S_MCLK or accept an external system clock input on
I2S_MCLK.
The sampling frequencies supported by the I
32 kHz, 44.1 kHz, and 48 kHz.
SPI Interface
FX3 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
2
2
C Interface
S Interface
2
SPI Timing Specification
C interface’s SCL and SDA signals require external pull-up
2
2
2
C controller supports bus frequencies of 100 kHz,
C interface is compatible with the I
C Master Controller also supports multi-master mode
2
C interface the flexibility to operate at a different
2
S port to support external audio codec devices.
2
2
2
C interface is capable of operating only as I
S Master as transmitter only. The I
C interface, as a selectable boot option.
2
C controller supports the clock-stretching
2
C interface is VIO5, which is a
on page 32 for details on the
CYUSB301X
2
C Bus Specification
Page 7 of 40
2
S interface are
2
S interface
2
2
C
C