S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 112
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S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.10
112
Address 0x0007 (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
DDRC
DDRD
Field
Field
Reset
7-0
7-0
W
R
Port C Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
Port D Data Direction—
This register controls the data direction of pins 7 through 0.
When used with the external bus this function controls the data direction for the associated pins. In this case the data
direction bits will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
DDRD7
Port D Data Direction Register (DDRD)
0
7
DDRD6
0
6
Figure 2-8. Port D Data Direction Register (DDRD)
Table 2-10. DDRC Register Field Descriptions
Table 2-11. DDRD Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
DDRD5
0
5
DDRD4
0
4
Description
Description
DDRD3
3
0
DDRD2
0
2
Access: User read/write
Freescale Semiconductor
DDRD1
0
1
DDRD0
0
0
(1)
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