DS1086LU-834/T&R Maxim Integrated, DS1086LU-834/T&R Datasheet - Page 5

• Manufacturer Part Number: DS1086LU-834/T&R
• Description: Programmable Oscillators
• Manufacturer: Maxim Integrated
• Series: DS1086r

Specifications of DS1086LU-834/T&R

• Part # Aliases: 90-1L86P-834

AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (continued)
(V
NONVOLATILE MEMORY CHARACTERISTICS
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Maxim Integrated
EEPROM Writes
Setup Time for STOP
Capacitive Load for Each Bus
Line
EEPROM Write Cycle Time
Input Capacitance
CC
CC
= 2.7V to 3.6V, T
= 2.7V to 3.6V)
PARAMETER
PARAMETER
All voltages are referenced to ground.
DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.
Correct operation of the device is not guaranteed if these limits are exceeded.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
This is the percentage frequency change from the +25°C frequency due to temperature at V
ature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequen-
cy (f
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two end-
points (f
This is true when the prescaler = 1.
Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original
value to the new value.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t
depends on the programmed clock frequency.
Output voltage swings can be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
1000ns + 250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
C
Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and three solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V
121°C/2 ATM Steam/Unbiased Autoclave.
t
is required before the frequency will be within its specified tolerance.
stab
A
B
—total capacitance of one bus line, timing referenced to 0.9 x V
= +25°C.
default
is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of t
CC
osc(MIN)
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/3.6V HAST and 168hr
). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz).
A
= -40°C to +85°C.)
HD:DAT
3.3V Spread-Spectrum EconOscillator
to f
osc(MAX)
need only be met if the device does not stretch the LOW period (t
SYMBOL
SYMBOL
t
SU:STO
) of the range. The error is in percentage of the span.
t
C
WR
C
B
I
+70°C
Fast mode
Standard mode
(Note 16)
stab
is equivalent to approximately 512 master clock cycles and therefore
CONDITIONS
CONDITIONS
CC
and 0.1 x V
CC
SU:DAT
.
10,000
MIN
MIN
0.6
4.0
LOW
CC
> 250ns must then be met.
= 3.3V. The maximum temper-
) of the SCL signal.
TYP
TYP
DS1086L
R MAX
5
IH MIN
+ t
MAX
MAX
400
10
SU:DAT
of the SCL
DACstab
UNITS
=
UNITS
ms
pF
pF
μs
5