MAX1180ECM-TD Maxim Integrated, MAX1180ECM-TD Datasheet - Page 5

• Manufacturer Part Number: MAX1180ECM-TD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1180ECM-TD

• Number Of Channels: 2
• Architecture: Pipeline
• Conversion Rate: 105 MSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 59 dB
• Interface Type: Parallel
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP EP
• Maximum Power Dissipation: 511 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 2
• Voltage Reference: Internal, External

ELECTRICAL CHARACTERISTICS (continued)
(V
10kΩ resistor, V
T
Note 1: Equivalent dynamic performance is obtainable over full OV
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a 1.024V full-scale
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
Note 5: Digital outputs settle to V
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
MAX
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse-Width High
CLK Pulse-Width Low
Wake-Up Time (Note 6)
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
DD
, unless otherwise noted. Typical values are at T
= 3.3V, OV
with Internal Reference and Parallel Outputs
input voltage range.
6dB or better, if referenced to the two-tone envelope.
PARAMETER
Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
IN
DD
= 2V
= 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
_______________________________________________________________________________________
P-P
(differential with respect to COM), C
IH
, V
SYMBOL
t
t
DISABLE
ENABLE
PDISS
IL
I
t
PSRR
OVDD
WAKE
t
t
. Parameter guaranteed by design.
t
DO
CH
CL
Operating, C
-0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Offset
Gain
Figure 3 (Note 5)
Figure 4
Figure 4
Figure 3, clock period: 9.5ns
Figure 3, clock period: 9.5ns
Wakeup from sleep mode
Wakeup from shutdown
f
f
f
INA or B
INA or B
INA or B
A
= +25°C.) (Note 2)
= 20MHz at -0.5dBFS
= 20MHz at -0.5dBFS
= 20MHz at -0.5dBFS
INA or B
L
L
= 15pF , f
CONDITIONS
= 10pF at digital outputs (Note 1), f
DD
= 20MHz at -0.5dBFS
range with reduced C
INA or B
= 20MHz at
DD
DD
L
.
MIN
CLK
= 105.263MHz, T
TYP
±0.2
±0.1
4.75
±1.5
4.75
±1.5
0.18
0.02
0.25
100
413
-70
9.2
1.5
1.5
15
10
2
3
5
MAX
±0.2
511
10
50
8
A
= T
degrees
UNITS
mV/V
mW
%/V
MIN
mA
µW
dB
dB
µA
ns
ns
ns
ns
ns
µs
to
5