MAX1180ECM-TD Maxim Integrated, MAX1180ECM-TD Datasheet - Page 14

• Manufacturer Part Number: MAX1180ECM-TD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1180ECM-TD

• Number Of Channels: 2
• Architecture: Pipeline
• Conversion Rate: 105 MSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 59 dB
• Interface Type: Parallel
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP EP
• Maximum Power Dissipation: 511 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 2
• Voltage Reference: Internal, External

where f
t
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1180 clock input operates with a voltage thresh-
old set to V
than 50%, must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1180
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
All digital outputs, D0A–D9A (Channel A) and D0B–D9B
(Channel B), are TTL/CMOS logic-compatible. There is
a five clock cycle latency between any particular sam-
ple and its corresponding output data. The output cod-
ing can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capaci-
tive load on the digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (< 15pF), to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1180, thereby degrading its
dynamic performance. Using buffers on the digital out-
puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1180 small-series
resistors (e.g., 100Ω), add to the digital output paths,
close to the MAX1180.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wake-up and data output valid.
The MAX1180 offers two power-save modes, sleep and
full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled) and current consumption is reduced to
2.8mA.
Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
14
AJ
is the time of the aperture jitter.
Digital Output Data, Output Data Format
______________________________________________________________________________________
IN
Power-Down (PD) and Sleep (SLEEP)
Selection (T/B), Output Enable (
represents the analog input frequency and
DD
/ 2. Clock inputs with a duty cycle other
System Timing Requirements
Modes
OE )
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high, forces
the digital outputs into a high-impedance state.
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers. The user
may select the R
performance to suit a particular application. For the
application in Figure 5, a R
the capacitive load to prevent ringing and oscillation.
The 22pF C
capacitor.
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully-differential signal, required by the MAX1180 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1180 provides better SFDR and
THD with fully-differential input signals, than a single-
ended drive, especially for high input frequencies. In
differential input mode, even-order harmonics are lower
as both inputs (INA+, INA- and/or INB+, INB-) are bal-
anced, and each of the ADC inputs only require half the
signal swing compared to single-ended mode.
Figure 4. Output Timing Diagram
D9A–D0A
D9B–D0B
OUTPUT
OUTPUT
OE
HIGH-Z
HIGH-Z
IN
Applications Information
capacitor acts as a small bypassing
ISO
t
ENABLE
Using Transformer Coupling
and C
DD
IN
/ 2 output voltage for level-
ISO
VALID DATA
VALID DATA
values to optimize the filter
of 50Ω is placed before
DD
/ 2 DC level shift to
HIGH-Z
HIGH-Z
t
DISABLE