MAX1033BEUP/GG8 Maxim Integrated, MAX1033BEUP/GG8 Datasheet - Page 22

• Manufacturer Part Number: MAX1033BEUP/GG8
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1033BEUP/GG8

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Snr: 85 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 879 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

8- and 4-Channel, ±3 x V
Multirange Inputs, Serial 14-Bit ADCs
The MAX1032/MAX1033 contain one byte-wide mode-
control register. The timing diagram of Figure 15 shows
how to use the mode-control byte, and the mode-con-
trol byte format is shown in Table 7. The mode-control
byte is used to select the conversion method and to
control the power modes of the MAX1032/MAX1033.
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or
Differential Input
Figure 14. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
22
______________________________________________________________________________________
3FFD
3FFF
3FFE
2001
2000
1FFF
0003
0002
0001
0000
3FFD
3FFF
3FFE
2001
2000
1FFF
0003
0002
0001
0000
(AGND1)
-8,192 -8,190
0
1
2
3
INPUT VOLTAGE (LSB [DECIMAL])
INPUT VOLTAGE (LSB [DECIMAL])
AGND1 (DIF/SGL = 0)
CH_- (DIF/SGL = 1)
-1
8,192
FSR
FSR
0
+1
1 LSB =
1 LSB =
16,384 x 4.096V
16,384 x 4.096V
FSR x V
FSR x V
Mode Control
16,381 16,383
+8,189 +8,191
REF
REF
REF
The conversion method is selected using the mode-
control byte (see the Mode Control section), and the con-
version is initiated using a conversion-start command
(Table 3, and Figures 2, 3, and 4).The MAX1032/
MAX1033 convert analog signals to digital data using one
of three methods:
•
•
•
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, -FSR to 0
External Clock Mode, Mode 0 (Figure 2)
• Highest maximum throughput (see the Electrical
• User controls the sample instant
• CS remains low during the conversion
• User supplies SCLK throughout the ADC con-
External Acquisition Mode, Mode 1 (Figure 3)
• Lowest maximum throughput (see the Electrical
• User controls the sample instant
• User supplies two bytes of SCLK, then drives
• After SSTRB transitions high, the user supplies
Internal Clock Mode, Mode 2 (Figure 4)
• High maximum throughput (see the Electrical
• The internal clock controls the sampling instant
3FFD
3FFF
3FFE
2001
2000
1FFF
0003
0002
0001
0000
Characteristics table)
version and reads data at DOUT
Characteristics table)
CS high to relieve processor load while the
ADC converts
two bytes of SCLK and reads data at DOUT
Characteristics table)
0
1
2
3
Selecting the Conversion Method
INPUT VOLTAGE (LSB [DECIMAL])
8,192
FSR
1 LSB =
16,384 x 4.096V
FSR x V
16,381 16,383
REF
(AGND1)