MAX1166BEUP-T Maxim Integrated, MAX1166BEUP-T Datasheet - Page 7

• Manufacturer Part Number: MAX1166BEUP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1166BEUP-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 165 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 90 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

MAX1165 MAX1166 MAX1165 MAX1166
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
—
Low-Power, 16-Bit Analog-to-Digital Converter
1
2
3
4
5
6
7
8
9
PIN
10
11
12
13
14
15
16
17
18
19
20
—
—
—
—
—
—
—
—
—
1
2
3
4
5
6
7
8
9
_______________________________________________________________________________________
D10
D11
D12
D13
D14
D15
D8
D9
D0
D1
D2
D3
D4
D5
D6
D7
REFADJ
RESET
NAME
AGND
AGND
DGND
HBEN
AV
DV
EOC
REF
R/C
AIN
CS
DD
DD
D4/D12
D5/D13
D6/D14
D7/D15
D2/D10
D3/D11
D0/D8
D1/D9
—
—
—
—
—
—
—
—
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output. D15 is the MSB.
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output (MSB)
Read/Convert Input. Power up and put the MAX1165/MAX1166 in acquisition mode
by holding R/C low during the first falling edge of CS. During the second falling
edge of CS, the level on R/C determines whether the reference and reference
buffer power down or remain on after conversion. Set R/C high during the second
falling edge of CS to power down the reference and buffer, or set R/C low to leave
the reference and buffer powered up. Set R/C high during the third falling edge of
CS to put valid data on the bus.
End of Conversion. EOC drives low when conversion is complete.
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
Analog Ground. Primary analog ground (star ground).
Analog Input
Analog Ground. Connect pin 14 to pin 12 (MAX1165). Connect pin 10 to pin 8
(MAX1166).
Refer ence Buffer Outp ut. Byp ass RE FAD J w i th a 0.1µF cap aci tor to AG N D for i nter nal
r efer ence m od e. C onnect RE FAD J to AV
Reference Input/Output. Bypass REF with a 4.7µF capacitor to AGND for internal
reference mode. External reference input when in external reference mode.
Reset Input. Logic high resets the device.
High-Byte Enable Input. Used to multiplex the 14-bit conversion result:
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
Convert Start. The first falling edge of CS powers up the device and enables
acquire mode when R/C is low. The second falling edge of CS starts conversion.
The third falling edge of CS loads the result onto the bus when R/C is high.
Digital Ground
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
with Parallel Interface
FUNCTION
D D
to sel ect exter nal r efer ence m od e.
Pin Description
7