ispLSI 3448-90LB432 Lattice, ispLSI 3448-90LB432 Datasheet - Page 6

• Manufacturer Part Number: ispLSI 3448-90LB432
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 3448-90LB432

• Product Category: CPLD - Complex Programmable Logic Devices
• Memory Type: EEPROM
• Number Of Macrocells: 256
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 224
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: BGA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 21
• Supply Current: 470 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

1. Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
PARAMETER
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Switching Characteristics
pd1
pd2
max
max (Ext.)
max (Tog.)
su1
co1
h1
su2
co2
h2
r1
rw1
ptoeen
ptoedis
goeen
goedis
toeen
toedis
wh
wl
su3
h3
COND.
TEST
C
C
C
A
A
A
–
–
–
A
–
–
–
–
A
–
B
B
B
–
–
–
–
5
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 Test OE Output Enable
19 Test OE Output Disable
20 Ext. Synchronous Clock Pulse Duration, High
21 Ext. Synchronous Clock Pulse Duration, Low
22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4)
23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4)
#
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay
3 Clock Frequency with Internal Feedback
4 Clock Frequency with External Feedback
5 Clock Frequency, Maximum Toggle
6 GLB Reg. Setup Time before Clock, 4 PT Bypass
7 GLB Reg. Clock to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
9 GLB Reg. Setup Time before Clock
2
Over Recommended Operating Conditions
1, 2, 3
DESCRIPTION
6
4
1
3
(
tsu2 + tco1
Specifications ispLSI 3448
1
)
MIN.
62.5
90.0
100
7.0
0.0
8.5
0.0
9.0
5.0
5.0
4.5
0.0
–
–
–
–
–
–
–
–
–
–
–
-90
MAX.
12.0
15.0
14.0
25.0
25.0
10.0
10.0
13.0
13.0
7.5
8.0
–
–
–
–
–
–
–
–
–
–
–
–
MIN.
70.0
50.0
83.0
11.0
12.0
9.0
0.0
0.0
6.0
6.0
5.0
0.0
–
–
–
–
–
–
–
–
–
–
–
-70
MAX.
15.0
18.0
10.0
15.0
30.0
30.0
12.0
12.0
15.0
15.0
9.0
–
–
–
–
–
–
–
–
–
–
–
–
Table 2-0030/3320
UNITS
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns