ispLSI 3448-90LB432 Lattice, ispLSI 3448-90LB432 Datasheet - Page 2

• Manufacturer Part Number: ispLSI 3448-90LB432
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 3448-90LB432

• Product Category: CPLD - Complex Programmable Logic Devices
• Memory Type: EEPROM
• Number Of Macrocells: 256
• Maximum Operating Frequency: 100 MHz
• Delay Time: 15 ns
• Number Of Programmable I/os: 224
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: BGA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 21
• Supply Current: 470 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

Figure 1. ispLSI 3448 Functional Block Diagram
RESET
Functional Block Diagram
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
TOE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
A0
A1
A2
A3
B0
B1
B2
B3
C0
C1
C2
C3
N3
D0
Output Routing Pool
Output Routing Pool
N2
D1
Input Bus
Input Bus
N1
D2
N0
D3
M3
E0
Output Routing Pool
Output Routing Pool
M2
E1
Input Bus
Input Bus
M1
E2
Global Routing Pool
M0
E3
(GRP)
2
L3
F0
Output Routing Pool
Output Routing Pool
L2
F1
Input Bus
Input Bus
Specifications ispLSI 3448
L1
F2
L0
F3
G0
K3
Output Routing Pool
Output Routing Pool
K2
G1
Input Bus
Input Bus
K1
G2
G3
K0
H3
H2
H1
H0
J3
J2
J1
J0
I3
I2
I1
I0
Boundary
Scan
0130/3448
TDI/SDI
TRST
TDO/SDO
I/O 159
I/O 158
I/O 157
I/O 156
I/O 155
I/O 154
I/O 153
I/O 152
I/O 151
I/O 150
I/O 149
I/O 148
I/O 147
I/O 146
I/O 145
I/O 144
I/O 143
I/O 142
I/O 141
I/O 140
I/O 139
I/O 138
I/O 137
I/O 136
I/O 135
I/O 134
I/O 133
I/O 132
I/O 131
I/O 130
I/O 129
I/O 128
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
I/O 122
I/O 121
I/O 120
I/O 119
I/O 118
I/O 117
I/O 116
I/O 115
I/O 114
I/O 113
I/O 112