MAX1362EUB-T Maxim Integrated, MAX1362EUB-T Datasheet - Page 19

• Manufacturer Part Number: MAX1362EUB-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1362EUB-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 689.7 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Table 9. Monitor-Mode Setup Data Format
Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format
Table 11. Delay Settings
* When using delay = [0,0,0] in internal reference mode and
AIN3/REF configured as a REF output, the MAX1361/MAX1362
may exhibit a code-dependant gain error due to insufficient
internal reference drive. Gain error caused by this phenomenon
is typically less than 1%FSR (0.1µF C
resistor) and increases with a larger C
by using an external reference, V
internal reference with AIN3/REF as an analog input (see Table
4). Alternatively, choose delay bits other than [0,0,0] to lower the
conversion rate.
Table 12. Lower and Upper Threshold Data Format
X = Don’t care.
ACK = Acknowledge.
ALARM CH 0
DELAY 2 DELAY 1 DELAY 0
Alarm reset, scan
4-Channel, 10-Bit, System Monitor with Programmable
speed, INT_EN ,
BYTE
RESET
0
0
0
0
1
1
1
1
1
2
3
0/1
(8 bits)
ALARM CH 1
0
0
1
1
0
0
1
1
UT7
LT3
B7
X
RESET
______________________________________________________________________________________
0/1
AIN0 thresholds
(24 bits)
0
1
0
1
0
1
0
1
UT6
LT2
B6
X
ALARM CH 2
DD
RESET
Trip Window and SMBus Alert Response
, as a reference or use an
0/1
REF
CONVERSION RATE
REF
MONITOR-MODE
(MSB)
(skip if differential mode, or
UT5
LT9
LT1
. Avoid this gain error
B5
in series with a 2k Ω
CS1, CS0 < 1) (24 bits)
(ksps)
150.0*
AIN1 thresholds
75.0
37.5
18.8
ALARM CH 3
9.4
4.7
2.3
1.2
RESET
LT0 (LSB)
0/1
UT4
LT8
B4
DELAY 2
UT3
LT7
B3
X
A 1 written to the reset alarm CH_ clears the alarm, oth-
erwise no action occurs (Table 10). Deassert INT by
clearing all alarms or by initiating an SMBus alert during
an alarm condition (see the SMBus Alert section)
The Delay 2, Delay 1, and Delay 0 bits set the speed of
monitoring by changing the delay between conver-
sions. Delay 2, 1, and 0 = 000 sets the maximum possi-
ble speed; 001 divides the maximum speed by
approximately 2. Increasing delay values further
divides the previous speed by two (Table 11).
INT_EN controls the open-drain INT output. Set INT_EN
to 1 to enable the hardware interrupt. Set INT_EN to 0
to disable the hardware interrupt output. The INT output
is high impedance when disabled or when there are no
alarms. The master can also poll the alarm status regis-
ter at any time to check the alarm status.
Repeat clocking channel threshold data up to the chan-
nel programmed by CS1 and CS0 (Table 12). For differ-
ential input mode, omit odd channels; the lower and
upper threshold data applies to channel pairs. There is
no need to clock in dummy data for odd (or even)
channels (Table 6).
0/1
AIN2 thresholds (skip if
CS1, CS0 < 2)
UT2
LT6
(24 bits)
B2
X
DELAY 1
0/1
(MSB)
UT9
UT1
LT5
B1
AIN3 thresholds (skip if differential
UT0 (LSB)
DELAY 0
mode, or CS1, CS0 < 3)
UT8
LT4
B0
0/1
(24 bits)
ACKNOWLEDGE
ACK
ACK
ACK
INT_EN
0/1
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